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| 型號(hào)： | M4LV-96/48-18VI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類(lèi)： | PLD |
| 英文描述： | High Performance E 2 CMOS In-System Programmable Logic |
| 中文描述： | EE PLD, 18 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 45/46頁(yè) |
| 文件大?。?/td> | 754K |
| 代理商： | M4LV-96/48-18VI |
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8MACH 4 Family
Table 6. Logic Allocator for All MACH 4 Devices (except M4(LV)-32/32)
Output Macrocell
Available Clusters
Output Macrocell
Available Clusters
M0
C0, C1, C2
M8
C7, C8, C9, C10
M1
C0, C1, C2, C3
M9
C8, C9, C10, C11
M2
C1, C2, C3, C4
M10
C9, C10, C11, C12
M3
C2, C3, C4, C5
M11
C10, C11, C12, C13
M4
C3, C4, C5, C6
M12
C11, C12, C13, C14
M5
C4, C5, C6, C7
M13
C12, C13, C14, C15
M6
C5, C6, C7, C8
M14
C13, C14, C15
M7
C6, C7, C8, C9
M15
C14, C15
Table 7. Logic Allocator for M4(LV)-32/32
Output Macrocell
Available Clusters
Output Macrocell
Available Clusters
M0
C0, C1, C2
M8
C8, C9, C10
M1
C0, C1, C2, C3
M9
C8, C9, C10, C11
M2
C1, C2, C3, C4
M10
C9, C10, C11, C12
M3
C2, C3, C4, C5
M11
C10, C11, C12, C13
M4
C3, C4, C5, C6
M12
C11, C12, C13, C14
M5
C4, C5, C6, C7
M13
C12, C13, C14, C15
M6
C5, C6, C7
M14
C13, C14, C15
M7
C6, C7
M15
C14, C15
0 Default
Prog. Polarity
To
n-1
To
n-2
From
n-1
To
n+1
From
n+1
From
n+2
Basic Product
Term Cluster
Extra
Product
Term
Logic Allocator
n
To
Macrocell
n
0 Default
Prog. Polarity
To
n-1
To
n-2
From
n-1
To
n+1
From
n+1
From
n+2
Basic Product
Term Cluster
Extra
Product
Term
Logic Allocator
nn
To
Macrocell
n
17466G-006
Figure 2. Logic Allocator: Conguration of Cluster “n” Set by Mode of Macrocell “n”
17466G-005
a. Synchronous Mode
b. Asynchronous Mode
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