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參數(shù)資料
| 型號： | M4LV-96/48-18VI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | High Performance E 2 CMOS In-System Programmable Logic |
| 中文描述： | EE PLD, 18 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 42/46頁 |
| 文件大?。?/td> | 754K |
| 代理商： | M4LV-96/48-18VI |
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MACH 4 Family
5
FUNCTIONAL DESCRIPTION
The fundamental architecture of MACH 4 devices (Figure 1) consists of multiple, optimized PAL
blocks interconnected by a central switch matrix. The central switch matrix allows
communication between PAL blocks and routes inputs to the PAL blocks. Together, the PAL
blocks and central switch matrix allow the logic designer to create large designs in a single
device instead of having to use multiple devices.
The key to being able to make effective use of these devices lies in the interconnect schemes.
In MACH 4 architecture, the macrocells are exibly coupled to the product terms through the
logic allocator, and the I/O pins are exibly coupled to the macrocells due to the output switch
matrix. In addition, more input routing options are provided by the input switch matrix. These
resources provide the exibility needed to t designs efciently.
Notes:
1. 16 for MACH 4 devices with 1:1 macrocell-I/O cell ratio (see next page).
2. Block clocks do not go to I/O cells in M4(LV)-32/32.
3. M4(LV)-192/96 and M4(LV)-256/128 have dedicated clock pins which cannot be used as inputs and do not connect to the central
switch matrix.
I/O
Pins
Clock/Input
Pins
Central
Switch
Matrix
I/O
Pins
I/O
Pins
Dedicated
Input Pins
PAL Block
Logic
Allocator
with XOR
Output/
Buried
Macrocells
33/
34/
36
16
Clock
Generator
Logic
Array
Output
Switch
Matrix
Input
Switch
Matrix
I/O
Cells
16
8
Note 1
Note 2
Note 3
4
PAL Block
17466G-001
Figure 1. MACH 4 Block Diagram and PAL Block Structure
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M4LV-96/48-7VC | High Performance E 2 CMOS In-System Programmable Logic |
| M4LV-256/128-10YI | High Performance E 2 CMOS In-System Programmable Logic |
| M4LV-64/32-18VI | High Performance E 2 CMOS In-System Programmable Logic |
| M4-256/128-12AC | High Performance E 2 CMOS In-System Programmable Logic |
| M4-256/128-12AI | High Performance E 2 CMOS In-System Programmable Logic |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M4M | 功能描述:XLR 連接器 4P ADAPT RECEPTACLE RoHS:否 制造商:Neutrik 標(biāo)準(zhǔn):Standard XLR 產(chǎn)品類型:Connectors 型式:Female 位置/觸點(diǎn)數(shù)量:3 端接類型:Solder 安裝風(fēng)格:Cable 方向:Vertical |
| M4-M | 制造商:Tamura Corporation of America 功能描述: |
| M4M/S SS PS | 制造商:NUTS 功能描述: |
| M4M/S ST ZC | 制造商:NUTS 功能描述: |
| M4M1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
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