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參數(shù)資料
| 型號： | M48T58Y-70PC1TR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDIP28 |
| 封裝： | 0.600 INCH, CAPHAT, PLASTIC, DIP-28 |
| 文件頁數(shù)： | 8/33頁 |
| 文件大小： | 511K |
| 代理商： | M48T58Y-70PC1TR |
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Clock operations
M48T58, M48T58Y
Doc ID 2412 Rev 7
Table 5.
Register map
Keys:
S = SIGN bit
FT = FREQUENCY TEST bit
R = READ bit
W = WRITE bit
ST = STOP bit
0 = Must be set to '0'
BLE = Battery low enable bit
BL = Battery low bit (read only)
CEB = Century enable bit
CB = Century bit
Note:
When CEB is set to '1,' CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century
(dependent upon the initial value set).
When CEB is set to '0,' CB will not toggle. The WRITE bit does not need to be set to write to
CEB.
6.4
Calibrating the clock
The M48T58/Y is driven by a quartz-controlled oscillator with a nominal frequency of 32,768
Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency
error at 25°C, which equates to about ±1.53 minutes per month. With the calibration bits
properly set, the accuracy of each M48T58/Y improves to better than +1/–2 ppm at 25°C.
The oscillation rate of any crystal changes with temperature (see Figure 8 on page 18).
Most clock chips compensate for crystal frequency and temperature shift error with
cumbersome “trim” capacitors. The M48T58/Y design, however, employs periodic counter
correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in Figure 9 on page 18. The number of times pulses
are blanked (subtracted, negative calibration) or split (added, positive calibration) depends
upon the value loaded into the five calibration bits found in the control register. Adding
counts speeds the clock up, subtracting counts slows the clock down.
The calibration byte occupies the five lower order bits (D4-D0) in the control register 1FF8h.
These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is the
Address
Data
Function/range
BCD format
D7
D6
D5
D4
D3
D2
D1
D0
1FFFh
10 Years
Year
00-99
1FFEh
0
10 M
Month
01-12
1FFDh
BLE
BL
10 date
Date
01-31
1FFCh
0
FT
CEB
CB
0
Day
Century/day
0-1/1-7
1FFBh
0
10 hours
Hours
00-23
1FFAh
0
10 minutes
Minutes
00-59
1FF9h
ST
10 seconds
Seconds
00-59
1FF8h
W
R
S
Calibration
Control
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M48T59V-70MH1E | 0 TIMER(S), REAL TIME CLOCK, PDSO28 |
| M48T59V-70PC1 | 0 TIMER(S), REAL TIME CLOCK, PDIP28 |
| M48T59Y-70PC1DS | 0 TIMER(S), REAL TIME CLOCK, PDIP28 |
| M48T59V-70MH1TR | 0 TIMER(S), REAL TIME CLOCK, PDSO28 |
| M48T59V-70MH1 | 0 TIMER(S), REAL TIME CLOCK, PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M48T58Y-70PC1TRE | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0V, 64 Kbit (8 Kb x 8) TIMEKEEPER SRAM |
| M48T58YMH | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Kbit 8Kb x8 TIMEKEEPER SRAM |
| M48T58YPC | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Kbit 8Kb x8 TIMEKEEPER SRAM |
| M48T58YSH | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Kbit 8Kb x8 TIMEKEEPER SRAM |
| M48T59 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Kbit 8Kb x8 TIMEKEEPER SRAM |
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