參數(shù)資料
型號(hào): M48T58Y-70MH1E
廠商: STMICROELECTRONICS
元件分類(lèi): 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO28
封裝: 0.330 INCH, ROHS COMPLIANT, PLASTIC, SOH-28
文件頁(yè)數(shù): 3/33頁(yè)
文件大?。?/td> 511K
代理商: M48T58Y-70MH1E
M48T58, M48T58Y
WRITE mode
Doc ID 2412 Rev 7
4
WRITE mode
The M48T58/Y is in the WRITE mode whenever W and E1 are low and E2 is high. The start
of a WRITE is referenced from the latter occurring falling edge of W or E1, or the rising edge
of E2. A WRITE is terminated by the earlier rising edge of W or E1, or the falling edge of E2.
The addresses must be held valid throughout the cycle. E1 or W must return high or E2 low
for a minimum of tE1HAX or tE2LAX from chip enable or tWHAX from WRITE enable prior to the
initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of
WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to
avoid bus contention; although, if the output bus has been activated by a low on E1 and G
and a high on E2, a low on W will disable the outputs tWLQZ after W falls.
Figure 6.
WRITE enable controlled, WRITE AC waveform
AI00963
tAVAV
tWHAX
tDVWH
DATA INPUT
A0-A12
E1
W
DQ0-DQ7
VALID
E2
tAVWH
tAVE1L
tAVE2H
tWLWH
tAVWL
tWLQZ
tWHDX
tWHQX
相關(guān)PDF資料
PDF描述
M48T58Y-70PC1TR 0 TIMER(S), REAL TIME CLOCK, PDIP28
M48T59V-70MH1E 0 TIMER(S), REAL TIME CLOCK, PDSO28
M48T59V-70PC1 0 TIMER(S), REAL TIME CLOCK, PDIP28
M48T59Y-70PC1DS 0 TIMER(S), REAL TIME CLOCK, PDIP28
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