參數(shù)資料
型號(hào): M48ST59W-100MH1
廠商: STMICROELECTRONICS
元件分類: 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO44
封裝: 0.330 INCH, SNAPHAT, PLASTIC, SOH-44
文件頁數(shù): 5/29頁
文件大?。?/td> 158K
代理商: M48ST59W-100MH1
13/29
M48ST59W
Data Retention Mode
With valid VCC applied, the M48ST59W operates
as a conventional BYTEWIDE static RAM.
Should the supply voltage decay, the RAM will au-
tomatically power-fail deselect, write protecting it-
self when VCC within the VPFD (max), VPFD (min)
window. All outputs become high impedance, and
all inputs are treated as “don’t care.”
Note: A power failure during a WRITE cycle may
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM’s con-
tent. At voltages below VPFD(min), the user can be
assured the memory will be in a write protected
state, provided the VCC fall time is not less than tF.
The M48ST59W may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. There-
fore, decoupling of the power supply lines is rec-
ommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48ST59W for
an accumulated period of tDR (at room tempera-
ture when VCC is less than VSO; see Table 9, page
14). As system power returns and VCC rises above
VSO, the battery is disconnected, and the power
supply is switched to external VCC. Normal RAM
operation can resume tREC after VCC reaches
VPFD(max).
For more information on Data Retention Storage
Life refer to the Application Note AN1012.
Figure 9. Power Down/Up Mode AC Waveforms
VCC
INPUTS
(PER CONTROL INPUT)
OUTPUTS
DON’T CARE
HIGH-Z
VALID
(PER CONTROL INPUT)
RECOGNIZED
VPFD (max)
VPFD (min)
VSO
RST
VALID
PFO
tFB
tDR
tF
tPD
tRB
tR
tREC
AI04605
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