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參數(shù)資料
| 型號： | M48ST59W-100MH1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO44 |
| 封裝： | 0.330 INCH, SNAPHAT, PLASTIC, SOH-44 |
| 文件頁數(shù)： | 11/29頁 |
| 文件大?。?/td> | 158K |
| 代理商： | M48ST59W-100MH1 |
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M48ST59W
Figure 11. Interrupt Reset Waveforms
Watchdog Timer
The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the eight-bit Watchdog Register (Ad-
dress 1FF7h). The five bits (BMB4-BMB0) store a
binary multiplier and the two lower order bits (RB1-
RB0) select the resolution, where 00 = 1/16 sec-
ond, 01 = 1/4 second, 10 = 1 second, and 11 = 4
seconds. The amount of time-out is then deter-
mined to be the multiplication of the five-bit multi-
plier value with the resolution. (For example:
writing 00001110 in the Watchdog Register = 3 x 1
or 3 seconds).
Note: Accuracy of timer is a function of the select-
ed resolution.
If the processor does not reset the timer within the
specified period, the M48ST59W sets the WDF
(Watchdog Flag) and generates a watchdog inter-
rupt or a microprocessor reset. The WDF is reset
by reading the Flags Register (Address 1FF0h).
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit. When set to a ’0,’ the
watchdog will activate the IRQ/FT pin when timed-
out. When WDS is set to a ’1,’ the watchdog will
output a negative pulse on the RST pin for a dura-
tion of 40ms to 200ms. The Watchdog register and
the FT Bit will reset to a ’0’ at the end of a watch-
dog time-out when the WDS Bit is set to a ’1.’
The watchdog timer resets when the microproces-
sor performs a re-write of the Watchdog Register.
The time-out period then starts over. Should the
watchdog timer time-out, a value of 00h needs to
be written to the Watchdog Register in order to
clear the IRQ/FT pin. This will also disable the
watchdog function until it is again programmed
correctly. A READ of the Flags Register will reset
the Watchdog Flag (D7, Register 1FF0h). The
watchdog function is automatically disabled upon
power-up and the Watchdog Register is cleared. If
the watchdog function is set to output to the IRQ/
FT pin and the frequency test function is activated,
the watchdog or alarm function prevails and the
frequency test function is denied.
Power-on Reset
The M48ST59W continuously
monitors VCC.
When VCC falls to the power fail detect trip point,
the RST pulls low (open drain) and remains low on
power-up for tREC (see Table 13, page 20) after
VCC passes VPFD. The RST pin is an open drain
output and an appropriate pull-up resistor should
be chosen to control rise time.
Battery Low Flag
The M48ST59W automatically performs periodic
battery voltage monitoring upon power-up and at
factory-programmed time intervals of 24 hours (at
day rollover) as long as the device is powered and
the oscillator is running. The Battery Low flag (BL),
Bit D4 of the Flags Register 1FF0h, will be assert-
ed high if the SNAPHAT battery is found to be
less than approximately 2.5V. The BL Flag will re-
main active until completion of battery replace-
ment and subsequent battery low monitoring tests,
either during the next power-up sequence or the
next scheduled 24-hour interval.
If a battery low is generated during a power-up se-
quence, this indicates that the battery voltage is
below 2.5V (approximately), which may be insuffi-
cient to maintain data integrity. Data should be
considered suspect and verified as correct. A fresh
battery should be installed.
15 ns Min
A0-A12
ACTIVE FLAG BIT
IRQ/FT
ADDRESS 1FF0h
HIGH-Z
AI04609
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