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參數(shù)資料
| 型號： | M470L3223DT0-CLB3 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256MB DDR SDRAM MODULE |
| 中文描述： | 256MB的DDR內(nèi)存模塊 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 171K |
| 代理商： | M470L3223DT0-CLB3 |
M470L3223DT0
Rev. 0.0 Dec. 2001
DDR SDRAM SPEC Items and Test Conditions
Recommended operating conditions Unless Otherwise Noted, T
A
=0 to 70
°
C
)
Conditions
Operating current - One bank Active-Precharge;
tRC=tRCmin;
DQ,DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle
Operating current - One bank operation ;
One bank open, BL=4, Reads
- Refer to the following page for detailed test condition
Percharge power-down standby current;
All banks idle; power - down mode;
CKE = <VIL(max); Vin = Vref for DQ,DQS and DM
Precharge Floating standby current;
CS# > =VIH(min);All banks idle;
CKE > = VIH(min); Address and other control inputs changing once per clock cycle;
Vin = Vref for DQ,DQS and DM
Precharge Quiet standby current;
CS# > = VIH(min); All banks idle;
CKE > = VIH(min);
Address and other control inputs stable with keeping >= VIH(min) or =<VIL(max);
Vin = Vref for DQ ,DQS and DM
Active power - down standby current ;
one bank active; power-down mode;
CKE=< VIL (max); Vin = Vref for DQ,DQS and DM
Active standby current;
CS# >= VIH(min); CKE>=VIH(min);
one bank active; active - precharge; tRC=tRASmax;
DQ, DQS and DM inputs changing twice per clock cycle;
address and other control inputs changing once per clock cycle
Operating current - burst read;
Burst length = 2; reads; continguous burst;
One bank active; address and control inputs changing once per clock cycle;
50% of data changing at every burst; lout = 0 m A
Operating current - burst write;
Burst length = 2; writes; continuous burst;
One bank active address and control inputs changing once per clock cycle;
DQ, DM and DQS inputs changing twice
per clock cycle, 50% of input data changing at every burst
Auto refresh current;
tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz and 12*tCK for DDR333; distributed refresh
Self refresh current;
CKE =< 0.2V; External clock should be on;
tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B and 166Mhz for DDR333
Orerating current - Four bank operation ;
Four bank interleaving with BL=4
-Refer to the following page for detailed test condition
Symbol
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7A
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| M470L3223DT0 | 256MB DDR SDRAM MODULE |
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