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參數(shù)資料
| 型號(hào)： | M470L3223DT0-CLA2 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256MB DDR SDRAM MODULE |
| 中文描述： | 256MB的DDR內(nèi)存模塊 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 171K |
| 代理商： | M470L3223DT0-CLA2 |
M470L3223DT0
Rev. 0.0 Dec. 2001
1. Maximum burst refresh of 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
4. For registered DINNs, t
CL
and t
CH
are
≥
45% of the period including both the half period jitter (t
JIT(HP)
) of the PLL and the half period
jitter due to crosstalk (t
JIT
(crosstalk)
) on the DIMM.
5. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time.
Parameter
Symbol
-TCB3(DDR333)
Unit
Note
Min
Max
Mode register set cycle time
tMRD
12
ns
Control & Address input pulse width
(for each input)
tIPW
2.2
ns
DQ & DM input pulse width(for each input)
tDIPW
1.75
ns
Exit self refresh to non read command
tXSNR
75
ns
Exit self refresh to read command
tXSRD
200
tCK
Refresh interval time
64Mb, 128Mb
tREFI
15.6
us
1
256Mb
7.8
us
1
Output DQS valid window
tQH
tHP-tQHS
-
ns
4
Clock half period
tHP
tCLmin
or tCHmin
-
ns
Data hold skew factor
tQHS
0.55
ns
DQS write postamble time
tRAP
tRCD or
tRAS min
ns
3
Auto Precharge Write recovery +
Precharge time
tDAL
(tWR/tCK) +
(tRP/tCK)
tCK
5
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