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參數資料
| 型號： | M470L3223DT0-CLA2 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256MB DDR SDRAM MODULE |
| 中文描述： | 256MB的DDR內存模塊 |
| 文件頁數： | 11/16頁 |
| 文件大小： | 171K |
| 代理商： | M470L3223DT0-CLA2 |
M470L3223DT0
Rev. 0.0 Dec. 2001
1. Maximum burst refresh of 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
4. A write command can be applied with t
RCD
satisfied after this command.
5. For registered DIMMs, t
CL
and t
CH
are
≥
45% of the period including both the half period jitter (t
JIT(HP)
) of the PLL and the half period
jitter due to crosstalk (t
JIT
(crosstalk)
) on the DIMM.
Parameter
Symbol
-TCA2(DDR266A)
-TCB0(DDR266B)
-TCA0 (DDR200)
Unit
Note
Min
Max
Min
Max
Min
Max
Mode register set cycle time
tMRD
15
15
16
ns
DQ & DM setup time to DQS
tDS
0.5
0.5
0.6
ns
7,8,9
DQ & DM hold time to DQS
tDH
0.5
0.5
0.6
ns
7,8,9
DQ & DM input pulse width
tDIPW
1.75
1.75
2
ns
Power down exit time
tPDEX
7.5
7.5
10
ns
Exit self refresh to non-Read command
tXSNR
75
75
80
ns
4
Exit self refresh to read command
tXSRD
200
200
200
tCK
Refresh interval time
64Mb, 128Mb
tREFI
15.6
15.6
15.6
us
1
256Mb
7.8
7.8
7.8
us
1
Output DQS valid window
tQH
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
ns
5
Clock half period
tHP
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
ns
Data hold skew factor
tQHS
0.75
0.75
0.8
ns
DQS write postamble time
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
3
Autoprecharge write recovery +
Precharge time
tDAL
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
tCK
11
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