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參數(shù)資料
| 型號(hào)： | M464S6554BTS-L7A |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | SDRAM Unbuffered SODIMM |
| 中文描述： | 內(nèi)存緩沖的SODIMM |
| 文件頁(yè)數(shù)： | 5/15頁(yè) |
| 文件大?。?/td> | 277K |
| 代理商： | M464S6554BTS-L7A |
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256MB, 512MB Unbuffered SODIMM
Rev. 1.2 March 2004
SDRAM
PIN CONFIGURATION DESCRIPTION
Pin
Name
Input Function
CLK
System clock
Active on the positive going edge to sample all inputs.
CS
Chip select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+t
SS
prior to valid command.
A0 ~ A12
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12
Column address : (x16 : CA0 ~ CA9)
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column address strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM0 ~ 7
Data input/output mask
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQ
0
~
63
Data input/output
Data inputs/outputs are multiplexed on the same pins.
V
DD
/V
SS
Power supply/ground
Power and ground for the input buffers and the core logic.
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| M4650-500 | 制造商:Manhattan Wire Products (MWP) 功能描述:SHLD MULTICOND CABLE, 40COND, 22AWG, 500FT, 300V; Reel Length (Imperial):500ft; Reel Length (Metric):152.4m; No. of Conductors:40; Conductor Size AWG:22AWG; Voltage Rating:300V; No. of Strands x Strand Size:7 x 30AWG ;RoHS Compliant: Yes |
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