
124
Atmel ATmega16/32/64/M1/C1 [DATASHEET]
7647K–AVR–12/13
14.9
PSC Input
For detailed information on the PSC, please refer to the Application Note “AVR138: PSC Cookbook”, available on the Atmel
web site.
Each module 0, 1 and 2 of PSC has its own system to take into account one PSC input. According to PSC module n input
a Retrigger or fault input.
Each block A or B is also configured by this PSC module n input control register (PMICn).
Figure 14-10. PSC Input Module
14.9.1 PSC Input Configuration
The PSC input configuration is done by programming bits in configuration registers.
14.9.1.1 Filter Enable
If the “Filter Enable” bit is set, a digital filter of 4 cycles is inserted before evaluation of the signal. The disable of this function is
mainly needed for prescaled PSC clock sources, where the noise cancellation gives too high latency.
Important: If the digital filter is active, the level sensitivity is true also with a disturbed PSC clock to deactivate the outputs
(emergency protection of external component). Likewise when used as fault input, PSC Module n Input A or Input B have to go
through PSC to act on PSCOUTn0/1/2 outputs. This way needs that CLKPSC is running. So thanks to PSC asynchronous output
control bit (PAOCnA/B), PSCINn input can desactivate directly the PSC outputs. Notice that in this case, input is still taken into
account as usually by input module system as soon as CLKPSC is running.
Figure 14-11. PSC Input Filterring
0
1
Digital
Filter
CLKPSC
PISELnA
(PISELnB)
Input
Processing
(retriggering)
Control
of the
6 outputs
PSC Core
(Counter,
Waveform
Generator,
...)
CLKPSC
0
2
4
PSCINn
PAOCnA (PAOCnB)
PELEVnA/PCAEnA
(PELEVnB/PCAEnB)
PRFMnA3:0
(PRFMnB3:0)
PSCOUTnA
PSCOUTnB
Analog
Comparator
n Output
1
PFLTEnA
(PFLTEnB)
CLKPSC
PSC Input
Module X
Output
Stage
Digital
Filter
4 x CLKPSC
PSCOUTnX
PIN
PSC Module n Input