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參數(shù)資料
| 型號： | M41T93ZQA6F |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | 1 TIMER(S), REAL TIME CLOCK, PQCC16 |
| 封裝： | 4 X 4 MM, ROHS COMPLIANT, QFN-16 |
| 文件頁數(shù)： | 3/49頁 |
| 文件大?。?/td> | 719K |
| 代理商： | M41T93ZQA6F |
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M41T93
Description
Doc ID 12615 Rev 5
1.1
SPI signal description
1.1.1
Serial data output (SDO)
The output pin is used to transfer data serially out of the memory. Data is shifted out on the
falling edge of the serial clock.
1.1.2
Serial data input (SDI)
The input pin is used to transfer data serially into the device. Instructions, addresses, and
the data to be written, are each received this way. Input is latched on the rising edge of the
serial clock.
1.1.3
Serial clock (SCL)
The serial clock provides the timing for the serial interface (as shown in Figure 19 on
page 40 and Figure 20 on page 40). The W/R bit, addresses, or data are latched, from the
input pin, on the rising edge of the clock input. The output data on the SDO pin changes
state after the falling edge of the clock input.
The M41T93 can be driven by a microcontroller with its SPI peripheral running in only mode
0: (CPOL, CPHA) = (0,0).
For this mode, input data (SDI) is latched in by the low-to-high transition of clock SCL, and
output data (SDO) is shifted out on the high-to-low transition of SCL (see Table 2 on
1.1.4
Chip enable (E)
When E is high, the memory device is deselected, and the SDO output pin is held in its high
impedance state.
After power-on, a high-to-low transition on E is required prior to the start of any operation.
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| M41T93RQA6F | 1 TIMER(S), REAL TIME CLOCK, PQCC16 |
| M41T93SQA6F | 1 TIMER(S), REAL TIME CLOCK, PQCC16 |
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| M43C505-XXX-Q44 | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC44 |
| M44C090-XXX-FL16 | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDSO16 |
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