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參數(shù)資料
| 型號： | M41T93ZQA6F |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | 1 TIMER(S), REAL TIME CLOCK, PQCC16 |
| 封裝： | 4 X 4 MM, ROHS COMPLIANT, QFN-16 |
| 文件頁數(shù)： | 22/49頁 |
| 文件大?。?/td> | 719K |
| 代理商： | M41T93ZQA6F |
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M41T93
Clock operation
Doc ID 12615 Rev 5
3.8.1
TI/TP
●
TI/TP = 0
IRQ/FT/OUT is active when TF is logic '1' (subject to the status of the timer interrupt
enable bit (TIE).
●
TI/TP = 1
IRQ/FT/OUT pulses active according to Table 8 (subject to the status of the TIE bit).
Note:
If an alarm condition, watchdog time-out, oscillator failure, or OUT = 0 cause IRQ/FT/OUT to
be asserted low, then IRQ/FT/OUT will remain asserted even if TI/TP is set to '1.' When in
pulse mode (TI/TP = 1), clearing the TF bit will not stop the pulses on IRQ/FT/OUT. The
output pulses will only stop if TE, TIE, or TI/TP are reset to '0.'
3.8.2
TF
At the end of a timer countdown, TF is set to logic '1.' If both timer and alarm interrupts are
required in the application, the source of the interrupt can be determined by reading the flag
bits. The timer will auto-reload and continue to count down regardless of the state of TF bit
(or TI/TP bit). The TF bit is cleared by reading the flags register.
3.8.3
TIE
In level mode (TI/TP = 0), when TF is asserted, the interrupt is asserted (if TIE = 1). To clear
the interrupt, the TF bit or the TIE bit must be reset.
3.8.4
TE
●
TE = 0
When the timer register (10h) is set to ‘0,’ the timer is disabled.
●
TE = 1
The timer is enabled. TE is reset (disabled) on power-down. When re-enabled, the
counter will begin from the same value as when it was disabled.
Table 8.
Interrupt operation (bit TI/TP = 1)
Source clock (Hz)
IRQ(1) period(s)
1.
TF and IRQ/FT/OUT become active simultaneously.
n(2) = 1
2.
n = loaded countdown timer value. The timer is stopped when n = 0.
n > 1
4096
1/8192
1/4096
64
1/128
1/64
1
1/64
1/60
1/64
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| M41T93RQA6F | 1 TIMER(S), REAL TIME CLOCK, PQCC16 |
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