參數(shù)資料
型號: M41T82ZQA6E
廠商: STMICROELECTRONICS
元件分類: 時鐘/數(shù)據(jù)恢復(fù)及定時提取
英文描述: 1 TIMER(S), REAL TIME CLOCK, QCC16
封裝: 4 X 4 MM, ROHS COMPLIANT, QFN-16
文件頁數(shù): 9/58頁
文件大小: 462K
代理商: M41T82ZQA6E
M41T82 M41T83
Operation
2.2
Read mode
In this mode the master reads the M41T8x slave after setting the slave address (see
Figure 13 on page 18). Following the WRITE Mode control bit (R/W = 0) and the
Acknowledge bit, the word address 'An' is written to the on-chip address pointer. Next the
START condition and slave address are repeated followed by the READ Mode control bit
(R/W = 1). At this point the master transmitter becomes the master receiver. The data byte
which was addressed will be transmitted and the master receiver will send an Acknowledge
bit to the slave transmitter. The address pointer is only incremented on reception of an
Acknowledge clock. The M41T8x slave transmitter will now place the data byte at address
An+1 on the bus, the master receiver reads and acknowledges the new byte and the
address pointer is incremented to “An+2.”
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter. The system-to-user transfer of clock data will be
halted whenever the address being read is a clock address (00h to 07h). The update will
resume due to a Stop Condition or when the pointer increments to any non-clock address
(08h-1Fh).
Note:
This is true both in READ Mode and WRITE Mode.
An alternate READ Mode may also be implemented whereby the master reads the M41T8x
slave without first writing to the (volatile) address pointer. The first address that is read is the
last one stored in the pointer (see Figure 14 on page 18).
Figure 12.
Slave address location
AI00602
R/W
SLAVE ADDRESS
START
A
0
100
0
11
MSB
LSB
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