參數(shù)資料
型號: M41T00AUDD1E
廠商: STMICROELECTRONICS
元件分類: 時鐘/數(shù)據(jù)恢復及定時提取
英文描述: REAL TIME CLOCK, DSO16
封裝: 5 X 4 MM, ROHS COMPLIANT, DFN-16
文件頁數(shù): 5/42頁
文件大小: 333K
代理商: M41T00AUDD1E
M41T00AUD
Operation
4.2
Characteristics
4.3
READ mode
In this mode, the master reads the M41T00AUD slave after setting the slave address (see
Figure 8). Following the WRITE mode control bit (R/W = 0) and the acknowledge bit, the
word (register) address An is written to the on-chip address pointer. Next the START
condition and slave address are repeated, followed by the READ mode control bit (R/W = 1).
At this point, the master transmitter becomes the master receiver. The data byte which was
addressed will be transmitted and the master receiver will send an acknowledge bit to the
slave transmitter. The address pointer is only incremented on reception of an acknowledge
bit. The device slave transmitter will now place the data byte at address An+1 on the bus.
The master receiver reads and acknowledges the new byte and the address pointer is
incremented to An+2.
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
An alternate READ mode may also be implemented, whereby the master reads the
M41T00AUD slave without first writing to the (volatile) address pointer. The first address
that is read is the last one stored in the pointer (see Figure 10).
Table 3.
AC characteristics
Symbol
Parameter(1)
1.
Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 3.0 to 3.6 V (except where noted).
Min
Typ
Max
Units
fSCL
SCL clock frequency
0
400
kHz
tLOW
Clock low period
1.3
s
tHIGH
Clock high period
600
ns
tR
SDA and SCL rise time
300
ns
tF
SDA and SCL fall time
300
ns
tHD:STA
START condition hold time
(after this period the first clock pulse is generated)
600
ns
tSU:STA
START condition setup time
(only relevant for a repeated start condition)
600
ns
tSU:DAT
(2)
2.
Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling
edge of SCL.
Data setup time
100
ns
tHD:DAT
Data hold time
0
s
tSU:STO
STOP condition setup time
600
ns
tBUF
Time the bus must be free before a new
transmission can start
1.3
s
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