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參數(shù)資料
| 型號(hào)： | M39832-B15WNE1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | TVS BI-DIR 30V 600W DO-15 |
| 中文描述： | 單芯片8兆1兆x8或512KB的x16閃存和256千位并行EEPROM存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 17/36頁(yè) |
| 文件大?。?/td> | 253K |
| 代理商： | M39832-B15WNE1T |
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Enable G High. Addresses are latched on the falling
edge of W, EE whichever occurs last.
Once initiated, the write operation is internally
timed until completion, that is during a time t
W
.
The status of the write operation can be found by
reading the Data Polling and Toggle bits (as de-
tailed in the READ chapter) or the ERB output. This
Ready/Busy output is driven low from the write of
the byte being written until the completion of the
internal Write sequence.
Write a Page in EEPROM Array
The Page write allows up to 64 bytes within the
same EEPROM page to be consecutively latched
into the memory prior to initiating a programming
cycle. All bytes must be located in a single page
address, that is A6-A14 when BYTE is high (x16)
or A5-A13 when BYTE is low (x8) must be the same
for all bytes. Once initiated, the Page write opera-
tion is internally timed until completion, that is dur-
ing a time t
WC
.
The status of the write operation can be seen by
reading the Data Polling and Toggle bits (as de-
tailed in the READ chapter) or the ERB output. This
Ready/Busy output is driven low from the write of
the first byte to be written until the completion of the
internal Write sequence.
A Page write is composed of successive Write
operations which must be sequenced within a time
period (between two consecutive Write operations)
that is smaller than the t
WLWL
value. If this period of
time exceeds the t
WLWL
value, the internal program-
ming cycle will start.
EEPROM Array Software Data Protection
A protection instruction allows the user to inhibit all
write modes to the EEPROM array: the Software
Data Protection (referenced as SDP in the follow-
ing). The SDP feature is useful for protecting the
EEPROM memory from inadvertent write cycles
that may occur during uncontrolled bus conditions.
The M39832 is shipped as standard in the unpro-
tected state meaning that the EEPROM memory
contents can be changed by the user. After the SDP
enable instruction, the device enters the Protect
Mode where no further write operations have any
effect on the EEPROM memory contents.
The device remains in this mode until a valid SDP
disable instruction is received whereby the device
reverts to the unprotected state.
To enable the Software Data Protection, the device
has to be written (with a Page Write) with three
specific data bytes at three specific memory loca-
tions (each location in a different page) as shown
in Figure 4 and Table 5B. This sequence provides
an unlock key to enable the write action, and, at the
same time, SDP continues to be set. Any further
Write in EEPROM when the SDP is set will use this
same sequence of three specific data bytes at three
specific memory locations followed by the bytes to
write. The first SDP enable sequence can be di-
rectly followed by the bytes to written.
Similarly, to disable the Software Data Protection
the user has to write specific data bytes into six
different locations with a Page Write addressing
different bytes in different pages, as shown in Fig-
ure 5 and Table 5B.
The Software Data Protection state is non-volatile
and is not changed by power on/off sequences. The
SDP enable/disable instructions set/reset an inter-
nal non-volatile bit and therefore will require a write
time t
WC
, This Write operation can be monitored
only on the Toggle bit (status bit DQ6) and the ERB
pin. The Ready/Busy output is driven low from the
first byte to be written (that is the first Write AAh,
@5555h of the SDP set/reset sequence) until the
completion of the internal Write sequence.
Write OTP Row
Writing (only one time) in the OTP row (64 bytes)
is enabled by an instruction (WOTP). This instruc-
tion is composed of three specific Write operations
of data bytes at three specific memory locations
(each location in a different page) followed by the
the data to store in the OTP row (refer to Table 5B).
When accessing the OTP row, the only LSB ad-
dresses are decoded and A6 must be ’0’. The LSB
addresses are A0 to A5 when BYTE = ’1’ (x16) and
A–1 to A4 when BYTE = ’0’ (x8). Once at least one
Byte of the OTP row has been written (even with
FFh), the whole row becomes Read only.
Write the EEPROM Block Identifier
The EEPROM block identifier (64 Bytes) can be
written with a single Write operation with A6 = ’0’
and the V
ID
level on A9 (see Table 6). When ac-
cessing the 64 Bytes of EEPROM Identifier, the
only LSB addresses are decoded. The LSB ad-
dresses are A0 to A5 when BYTE = ’1’ (x16) and
A-1 to A4 when BYTE = ’0’ (x8). Each Byte of the
EEPROM identifier can be individually accessed in
read or write mode.
PROGRAM in the Flash ARRAY
It should be noted that writing data into the
EEPROM array and the Flash array is not per-
formed in a similar way: the Flash memory requires
an instruction (see Instruction chapter) for Erasing
and another instruction for Programming one (or
more) byte(s) or word(s), the EEPROM memory is
directly written with a simple operation (see Opera-
tion chapter).
17/36
M39832
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PDF描述 |
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| M39832-T12WNE6T | TVS UNI-DIR 33V 600W DO-15 |
| M39832-T15WNE6T | TVS BI-DIR 33V 600W DO-15 |
| M39832-B12WNE6T | RECTIFIER, BRIDGE, 600V, 6A, PB-6 |
| M39832-B15WNE6T | TVS UNI-DIR 51V 600W DO-15 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M39832-B15WNE6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Single Chip 8 Mbit 1Mb x8 or 512Kb x16 Flash and 256 Kbit Parallel EEPROM Memory |
| M39832NE | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Single Chip 8 Mbit 1Mb x8 or 512Kb x16 Flash and 256 Kbit Parallel EEPROM Memory |
| M39832-T12WNE1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Single Chip 8 Mbit 1Mb x8 or 512Kb x16 Flash and 256 Kbit Parallel EEPROM Memory |
| M39832-T12WNE6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Single Chip 8 Mbit 1Mb x8 or 512Kb x16 Flash and 256 Kbit Parallel EEPROM Memory |
| M39832-T15WNE1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Single Chip 8 Mbit 1Mb x8 or 512Kb x16 Flash and 256 Kbit Parallel EEPROM Memory |
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