參數(shù)資料
型號： M38749MFT-XXXGP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機
文件頁數(shù)： 17/92頁
文件大?。?/td> 1292K
代理商： M38749MFT-XXXGP
24
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
INT0
INT1
Receive bus
interrupt source 1
Receive bus
interrupt source 2
Receive bus
interrupt source 3
Transmit bus
interrupt source 1
Transmit bus
interrupt source 2
Transmit bus
interrupt source 3
Timer X
Timer Y
Timer 2
Timer 3
INT2
Serial I/O3
interrupt
CNTR0
CNTR1
Timer 1
INT3
INT4
INT5
ADT
A-D converter
Serial I/O2
interrupt
Key input (key-
on wake-up)
Serial I/O1
receive
Serial I/O1
transmit
BRK instruction
Interrupt Request
Generating Conditions
Remarks
Interrupt Sources
Low
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
High
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Table 7 Interrupt vector addresses and priority
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
3: Either ADT interrupt or A-D converter interrupt can be used. Both ADT interrupt and A-D converter interrupt cannot be used.
Vector Addresses (Note 1)
Reset (Note 2)
At reset
At detection of either rising or
falling edge of INT0 input
At detection of either rising or
falling edge of INT1 input
When receive bus interrupt
source 1 request bit becomes
“1” from “0”
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
The condition which the receive
bus interrupt factor request bit
becomes “1” is defined according
to each communication protocol
specification confirmation.
The condition which the transmit
bus interrupt factor request bit
becomes “1” is defined according
to each communication protocol
specification confirmation.
External interrupt
(active edge selectable)
Valid only when serial I/O3 is
selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid only when ADT interrupt is
selected
External interrupt
(falling valid)
Valid only when A-D converter
interrupt is selected
Valid only when serial I/O2 is
selected
External interrupt
(falling valid)
Valid only when serial I/O1 is
selected
Valid only when serial I/O1 is
selected
Non-maskable software interrupt
When receive bus interrupt
source 2 request bit becomes
“1” from “0”
When receive bus interrupt
source 3 request bit becomes
“1” from “0”
When transmit bus interr upt
source 1 request bit becomes
“1” from “0”
When transmit bus interr upt
source 2 request bit becomes
“1” from “0”
When transmit bus interr upt
source 3 request bit becomes
“1” from “0”
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
At detection of either rising or
falling edge of INT2 input
At completion of serial I/O3 data
transmission/reception
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
At timer 1 underflow
At detection of either rising or
falling edge of INT3 input
At detection of either rising or
falling edge of INT4 input
At detection of either rising or
falling edge of INT5 input
At falling of ADT pin input
At completion of A-D converter
At completion of serial I/O2 data
transmission/reception
At falling of port P20 to P25 (at
input) input logical level AND
At completion of serial I/O1 data
reception
At completion of serial I/O1
transmission shift or when
transmission buffer is empty
At BRK instruction execution
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