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APPLICATION
2.4 Timer 1, timer 2, and timer 3
3822 GROUP USER’S MANUAL
2–94
(3) Interrupt request register 1 (IREQ1) and interrupt request register 2 (IREQ2)
The interrupt request register 1 (address 003C16) and the interrupt request register 2 (address 003D16)
indicate whether an interrupt request has occured or not.
Figure 2.4.9 shows the structure of the interrupt request register 1 and Figure 2.4.10 shows the
structure of the interrupt request register 2.
The occurrence of an interrupt request causes the corresponding bit to be set to “1.” This interrupt
request bit is automatically cleared to “0” by the acceptance of the interrupt request.
The interrupt request bit can be cleared to “0” by software, but it cannot be set to “1” by software.
The occurrence of each interrupt is controlled by the interrupt enable bit (refer to the next item).
For details of interrupts, refer to “2.2 Interrupts.”
Fig. 2.4.9 Structure of interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address 3C 16]
B
Name
Functions
At reset R W
Interrupt request register 1
0
0 : No interrupt request issued
1 : Interrupt request issued
0
V
INT0 interrupt request
bit
1
INT1 interrupt request
bit
0
2
Serial I/O receive
interrupt request bit
0
3
Serial I/O transmit
interrupt request bit
0
V
: “0” can be set by software, but “1” cannot be set.
4
Timer X interrupt
request bit
0
5
Timer Y interrupt
request bit
0
6
Timer 2 interrupt
request bit
0
7
Timer 3 interrupt
request bit
0
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
V