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參數(shù)資料
| 型號： | M381L5623MTM-CA2 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DDR SDRAM Unbuffered Module |
| 中文描述： | DDR SDRAM的緩沖模塊 |
| 文件頁數(shù)： | 10/17頁 |
| 文件大小： | 250K |
| 代理商： | M381L5623MTM-CA2 |
Preliminary
DDR SDRAM
2GB Unbuffered DIMM
Rev. 0.0 April 2004
AC Timing Parameters & Specifications
Parameter
Symbol
B3
(DDR333@CL=2.5))
Min
A2
(DDR266@CL=2.0)
Min
B0
(DDR266@CL=2.5))
Min
Unit
Note
Max
Max
Max
Row cycle time
tRC
60
65
65
ns
Refresh row cycle time
tRFC
120
120
120
ns
Row active time
tRAS
42
70K
45
120K
45
120K
ns
RAS to CAS delay
tRCD
18
20
20
ns
Row precharge time
tRP
18
20
20
ns
Row active to Row active delay
tRRD
12
15
15
ns
Write recovery time
tWR
15
15
15
ns
Last data in to Read command
tWTR
1
1
1
tCK
Col. address to Col. address delay
tCCD
1
1
1
tCK
Clock cycle time
CL=2.0
tCK
7.5
12
7.5
12
10
12
ns
CL=2.5
6
12
7.5
12
7.5
12
ns
Clock high level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock low level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
DQS-out access time from CK/CK
tDQSCK
-0.6
+0.6
-0.75
+0.75
-0.75
+0.75
ns
Output data access time from CK/CK
tAC
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
Data strobe edge to output data edge
tDQSQ
-
0.45
-
0.5
-
0.5
ns
12
Read Preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read Postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
CK to valid DQS-in
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS-in setup time
tWPRES
0
0
0
ns
3
DQS-in hold time
tWPRE
0.25
0.25
0.25
tCK
DQS falling edge to CK rising-setup time
tDSS
0.2
0.2
0.2
tCK
DQS falling edge from CK rising-hold time
tDSH
0.2
0.2
0.2
tCK
DQS-in high level width
tDQSH
0.35
0.35
0.35
tCK
DQS-in low level width
tDQSL
0.35
0.35
0.35
tCK
DQS-in cycle time
tDSC
0.9
1.1
0.9
1.1
0.9
1.1
Address and Control Input setup time(fast)
tIS
0.75
0.9
0.9
ns
i,5.7~9
Address and Control Input hold time(fast)
tIH
0.75
0.9
0.9
ns
i,5.7~9
Address and Control Input setup time(slow)
tIS
0.8
1.0
1.0
ns
i, 6~9
Address and Control Input hold time(slow)
tIH
0.8
1.0
1.0
ns
i, 6~9
Data-out high impedance time from CK/CK
tHZ
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
1
Data-out low impedance time from CK/CK
tLZ
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
1
Output Slew Rate Matching Ratio(rise to fall)
tSLMR
0.67
1.5
0.67
1.5
0.67
1.5
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