參數(shù)資料
型號： M38079MF-172FP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 64/74頁
文件大小： 1182K
代理商： M38079MF-172FP
64
MITSUBISHI MICROCOMPUTERS
3807 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS
Table 18 Timing requirements (1)
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = – 20 to 85
°
C, unless otherwise noted)
Min.
2
125
50
50
200
80
80
80
80
800
370
370
220
100
1000
400
400
200
200
Typ.
Max.
Symbol
Parameter
Limits
Unit
t
W
(RESET)
t
C
(X
IN
)
t
WH
(X
IN
)
t
WL
(X
IN
)
t
C
(CNTR)
t
WH
(CNTR)
t
WL
(CNTR)
t
WH
(INT)
t
WL
(INT)
t
C
(S
CLK1
)
t
WH
(S
CLK1
)
t
WL
(S
CLK1
)
t
su
(R
X
D–S
CLK1
)
t
h
(S
CLK1
–R
X
D)
t
C
(S
CLK2
)
t
WH
(S
CLK2
)
t
WL
(S
CLK2
)
t
su
(S
IN2
–S
CLK2
)
t
h
(S
CLK2
–S
IN2
)
Note:
When bit 6 of address 001A
16
is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A
16
is “0” (UART).
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR
0
, CNTR
1
input cycle time
CNTR
0
, CNTR
1
input “H” pulse width
CNTR
0
, CNTR
1
input “L” pulse width
INT
0
to INT
4
input “H” pulse width
INT
0
to INT
4
input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 clock input set up time
Serial I/O1 clock input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 clock input set up time
Serial I/O2 clock input hold time
Max.
Symbol
Parameter
Unit
Min.
2
243
100
100
500
230
230
230
230
2000
950
950
400
200
2000
950
950
400
300
Typ.
t
W
(RESET)
t
C
(X
IN
)
t
WH
(X
IN
)
t
WL
(X
IN
)
t
C
(CNTR)
t
WH
(CNTR)
t
WL
(CNTR)
t
WH
(INT)
t
WL
(INT)
t
C
(S
CLK1
)
t
WH
(S
CLK1
)
t
WL
(S
CLK1
)
t
su
(R
X
D–S
CLK1
)
t
h
(S
CLK1
–R
X
D)
t
C
(S
CLK2
)
t
WH
(S
CLK2
)
t
WL
(S
CLK2
)
t
su
(S
IN2
–S
CLK2
)
t
h
(S
CLK2
–S
IN2
)
Note:
When bit 6 of address 001A
16
is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A
16
is “0” (UART).
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR
0
, CNTR
1
input cycle time
CNTR
0
, CNTR
1
input “H” pulse width
CNTR
0
, CNTR
1
input “L” pulse width
INT
0
to INT
4
input “H” pulse width
INT
0
to INT
4
input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 clock input set up time
Serial I/O1 clock input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 clock input set up time
Serial I/O2 clock input hold time
Table 19 Timing requirements (2)
(Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = – 20 to 85
°
C, unless otherwise noted)
Limits
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