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參數(shù)資料
| 型號： | M38079MF-172FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 40/74頁 |
| 文件大?。?/td> | 1182K |
| 代理商： | M38079MF-172FP |
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40
MITSUBISHI MICROCOMPUTERS
3807 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
G
Serial I/O2
The serial I/O2 can be operated only as the clock synchronous
type. As a synchronous clock for serial transfer, either internal clock
or external clock can be selected by the serial I/O2 synchronous
clock selection bit (b6) of serial I/O2 control register 1.
The internal clock incorporates a dedicated divider and permits
selecting 6 types of clock by the internal synchronous clock selec-
tion bit (b2, b1, b0) of serial I/O2 control register 1.
Regarding S
OUT2
and S
CLK2
being output pins, either CMOS output
format or N-channel open-drain output format can be selected by
the P7
1
/S
OUT2
, P7
2
/S
CLK2
P-channel output disable bit (b7) of
serial I/O2 control register 1.
When the internal clock has been selected, a transfer starts by a
write signal to the serial I/O2 register (address 001F
16
). After comple-
tion of data transfer, the level of the S
OUT2
pin goes to high imped-
ance automatically but bit 7 of the serial I/O2 control register 2 is
not set to "1" automatically.
When the external clock has been selected, the contents of the
serial I/O2 register is continuously sifted while transfer clocks are
input. Accordingly, control the clock externally. Note that the S
OUT2
pin does not go to high impedance after completion of data trans-
fer.
To cause the S
OUT2
pin to go to high impedance in the case where
the external clock is selected, set bit 7 of the serial I/O2 control
register 2 to "1" when S
CLK2
is "H" after completion of data transfer.
After the next data transfer is started (the transfer clock falls), bit 7
of the serial I/O2 control register 2 is set to "0" and the S
OUT2
pin is
put into the active state.
Regardless of the internal clock to external clock, the interrupt re-
quest bit is set after the number of bits (1 to 8 bits) selected by the
optional transfer bit is transferred. In case of a fractional number of
bits less than 8 bits as the last data, the received data to be stored
in the serial I/O2 register becomes a fractional number of bits close
to MSB if the transfer direction selection bit of serial I/O2 control
register 1 is LSB first, or a fractional number of bits close to LSB if
the said bit is MSB first. For the remaining bits, the previously re-
ceived data is shifted.
At transmit operation using the clock synchronous serial I/O, the
S
CMP2
signal can be output by comparing the state of the transmit
pin S
OUT2
with the state of the receive pin S
IN2
in synchronization
with a rise of the transfer clock. If the output level of the S
OUT2
pin is
equal to the input level to the S
IN2
pin, "L" is output from the S
CMP2
pin. If not, "H" is output. At this time, an INT
2
interrupt request can
also be generated. Select a valid edge by bit 2 of the interrupt edge
selection register (address 003A
16
).
[Serial I/O2 Control Registers 1, 2] SIO2CON1 / SIO2CON2
The serial I/O2 control registers 1 and 2 are containing various se-
lection bits for serial I/O2 control as shown in Figure 40.
Fig. 38 Structure of Serial I/O2 control registers 1, 2
Serial I/O2 control register 1
(SIO2CON1 : address 001D
16
)
Serial I/O2 control register 2
16
)
Optional transfer bits
0 0 0: 1 bit
0 0 1: 2 bit
0 1 0: 3 bit
0 1 1: 4 bit
1 0 0: 5 bit
1 0 1: 6 bit
1 1 0: 7 bit
1 1 1: 8 bit
b7
b7 b0
Not used ( returns "0" when read)
Serial I/O2 I/O comparison signal control bit
1
I/O
1: S
CMP2
output
S
pin control bit (P7
1
)
0: Output active
1: Output high-impedance
Internal synchronous clock selection bit
0 0 0: f(X
IN
)/8 (f(X
CIN
)/8 in low-speed mode)
0 0 1: f(X
IN
)/16 (f(X
CIN
)/16 in low-speed mode)
0 1 0: f(X
IN
)/32 (f(X
CIN
)/32 in low-speed mode)
0 1 1: f(X
IN
)/64 (f(X
CIN
)/64 in low-speed mode)
1 1 0: f(X
IN
)/128 f(X
CIN
)/128 in low-speed mode)
1 1 1: f(X
IN
)/256 (f(X
CIN
)/256 in low-speed mode)
Serial I/O2 port selection bit
0: I/O port
1: S
OUT2
,S
CLK2
output pin
S
output enable bit
0: P7
3
pin is normal I/O pin
1: P7
3
pin is S
RDY2
output pin
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O2 synchronous clock selection bit
0: External clock
P7
/S
P7
/S
P-channel output disable bit
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode )
b0
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