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參數(shù)資料
| 型號： | M38073M4-218FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Low-Power Configurable Multiple-Function Gate 6-SOT-23 -40 to 85 |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 66/74頁 |
| 文件大?。?/td> | 1182K |
| 代理商： | M38073M4-218FP |
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66
MITSUBISHI MICROCOMPUTERS
3807 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
φ
clock cycle time
φ
clock “H” pulse width
φ
clock “L” pulse width
AD
15
–AD
8
delay time
AD
7
–AD
0
delay time
AD
15
–AD
8
valid time
AD
7
–AD
0
valid time
SYNC delay time
SYNC valid time
Data bus delay time
Data bus valid time
RD pulse width, WR pulse width
RD pulse width, WR pulse width
(When one-wait is valid)
AD
15
–AD
8
delay time
AD
7
–AD
0
delay time
AD
15
–AD
8
valid time
AD
7
–AD
0
valid time
Data bus delay time
Data bus valid time
RESET
OUT
output delay time
RESET
OUT
output valid time (Note)
Min.
Symbol
Limits
Typ.
2t
C
(X
IN
)
Test conditions
t
c(
φ
)
t
WH
(
φ
)
t
WL
(
φ
)
t
d(
φ
–AH)
t
d(
φ
–AL)
t
v(
φ
–AH)
t
v(
φ
–AL)
t
d(
φ
–SYNC)
t
v(
φ
–SYNC)
t
d(
φ
–DB)
t
v(
φ
–DB)
t
WL
(RD)
, t
WL
(WR)
t
d(AH–RD)
, t
d(AH–WR)
t
d(AL–RD)
, t
d(AL–WR)
t
v(RD–AH)
, t
v(WR–AH)
t
v(RD–AL)
, t
v(WR–AL)
t
d(WR–DB)
t
v(WR–DB)
_____
t
d(RESET–RESET
OUT
)
t
v(
φ
–RESET
OUT
)
Note:
The
RESET
OUT
output goes “H” in sync with the fall of the
φ
clock that is anywhere between about 8 cycle and 13 cycles after the
RESET
input goes “H”.
____________
Max.
16
20
5
5
16
5
15
t
C
(X
IN
)–16
t
C
(X
IN
)–20
5
5
15
t
C
(X
IN
)–10
t
C
(X
IN
)–10
2
2
10
t
C
(X
IN
)–10
3t
C
(X
IN
)–10
t
C
(X
IN
)–35
t
C
(X
IN
)–40
2
2
10
0
35
40
30
30
200
100
Parameter
Fig. 3.1.1
TIMING REQUIREMENTS IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
SWITCHING CHARACTERISTICS IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
t
su(ONW–
φ
)
t
h(
φ
–ONW)
t
su(DB–
φ
)
t
h(
φ
–DB)
t
su(ONW–RD),
t
su(ONW–WR)
t
h(RD–ONW)
, t
h(WR–ONW)
t
su(DB–RD)
t
h(RD–DB)
_________
_________
Data bus set up time
Data bus hold time
ONW input set up time
_________
Data bus set up time
Data bus hold time
Min.
–20
–20
50
0
–20
–20
50
0
Typ.
Max.
Symbol
Parameter
Limits
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Table 22 Timing requirements in memory expansion and microprocessor mode(1)
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = – 20 to 85
°
C, in high-speed mode, unless otherwise noted)
Table 23 Switching characteristics in memory expansion and microprocessor mode(1)
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = – 20 to 85
°
C, in high-speed mode, unless otherwise noted)
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