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參數(shù)資料
| 型號： | M38073M4-218FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Low-Power Configurable Multiple-Function Gate 6-SOT-23 -40 to 85 |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 43/74頁 |
| 文件大?。?/td> | 1182K |
| 代理商： | M38073M4-218FP |
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43
3807 Group
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D Converter
[A-D Conversion Register] AD (address 0035
16
)
The A-D conversion register is a read-only register that contains the
result of an A-D conversion. When reading this register during an
A-D conversion, the previous conversion result is read.
[A-D Control Register] ADCON
The A-D control register controls the A-D conversion process. Bits 0
to 3 of this register select specific analog input pins. Bit 4 signals the
completion of an A-D conversion. The value of this bit remains at "0"
during an A-D conversion, then changes to "1" when the A-D conver-
sion is completed. Writing "0" to this bit starts the A-D conversion.
When bit 6, which is the AD external trigger valid bit, is set to "1", this
bit enables A-D conversion at a falling edge of an ADT input. Set
ports which is also used as ADT pins to input when using an A-D
external trigger. Bit 5 is the ADV
REF
input switch bit. Writing "1" to
this bit, this bit always causes ADV
REF
connection. Writing "0" to this
bit causes ADV
REF
connection only during A-D conversion and cut
off when A-D conversion is completed.
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between AV
SS
and ADV
REF
by 256, and outputs the divided voltages.
[Channel Selector]
The channel selector selects one of the input ports AN
12
to AN
0
and
inputs it to the comparator.
[Comparator and Control Circuit]
The comparator and control circuit compares an analog input
voltage with the comparison voltage and stores the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
conversion interrupt request bit to "1."
Note that the comparator is constructed linked to a capacitor, so set
f(X
IN
) to at least 500kHz during A-D conversion. Use a CPU system
clock dividing the main clock X
IN
as the internal clock
φ
.
I
Note
When the A-D external trigger is invalidated by the AD external
trigger valid bit, any interrupt request is not generated at a fall of the
ADT input. When the AD external trigger valid bit is set to "1" before-
hand, A-D conversion is not started by writing "0" into the AD conver-
sion completion bit and "0" is not written into the AD conversion
completion bit. Do not set "0" in the AD conversion completion bit
concurrently with the timing at which the AD external trigger valid bit
is rewritten. Put an interval of at least 50 cycles to more of the
internal clock
φ
between a start of A-D conversion and the next start
of A-D conversion.
A-D control register
16
)
Analog input pin selection bit
3
/S
RDY2
/ADT/AN
0
4
1
5
2
6
3
7
4
0
5
1
6
2
7
3
IN
/AN
8
4
REF
9
5
REF
/AN
10
0
3
11
0001: P7
1
/AN
4
/AN
12
AD conversion completion bit
0: Conversion in progress
REF
input switch bit
ADV
AD external trigger valid bit
Interrupt source selection bit
1: Interrupt request at ADT
b7
b0
A-D control register
C
A-D control circuit
A-D conversion register
8
Resistor ladder
AV
SS
ADV
REF
Comparator
ADT/A-D interrupt request
b7
b0
Data bus
4
P7
3
/S
RDY2
/ADT/AN
0
P7
4
/AN
1
P7
5
/AN
2
P7
6
/AN
3
P7
7
/AN
4
P6
0
/AN
5
P6
1
/AN
6
P6
2
/AN
7
P6
3
/CMP
IN
/AN
8
P6
4
/CMP
REF
/AN
9
P6
5
/DAV
REF
/AN
10
P8
0
/DA
3
/AN
11
P8
1
/DA
4
/AN
12
Fig. 42. Structure of A-D control register
Fig. 43. Block diagram of A-D converter
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