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參數(shù)資料
| 型號： | M3806 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Single Chip 8 Bits Microcomputer(8位單片機) |
| 中文描述： | 單芯片8位單片機（8位單片機） |
| 文件頁數(shù)： | 52/57頁 |
| 文件大?。?/td> | 833K |
| 代理商： | M3806 |
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52
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Before
After
φ
ONW input hold time
Before
φ
data bus set up time
After
φ
data bus hold time
Before RD ONW input set up time
___
_____
Before WR ONW input set up time
After RD ONW input hold time
___
_____
After WR ONW input hold time
Before RD data bus set up time
After RD data bus hold time
t
su(ONW–
φ
)
t
h(
φ
–ONW)
t
su(DB–
φ
)
t
h(
φ
–DB)
t
su
(ONW–RD)
t
su
(ONW–WR)
t
h(RD–ONW)
t
h(WR–ONW)
t
su(DB–RD)
t
h(RD–DB)
Symbol
Parameter
Limits
Typ.
Min.
–20
–20
120
ns
ns
ns
ns
ns
ns
ns
ns
Unit
0
–20
–20
120
0
Max.
φ
clock cycle time
φ
clock “H” pulse width
φ
clock “L” pulse width
AD
15
–AD
8
delay time
AD
15
–AD
8
valid time
AD
7
–AD
0
delay time
AD
7
–AD
0
valid time
SYNC delay time
SYNC valid time
Data bus delay time
RD pulse width, WR pulse width
(when one-wait is valid)
After AD
15
–AD
8
RD delay time
After AD
15
–AD
8
After AD
7
–AD
0
RD delay time
After AD
7
–AD
0
WR delay time
After RD AD
15
–AD
8
valid time
After WR AD
15
–AD
8
valid time
After RD AD
7
–AD
0
valid time
After WR AD
7
–AD
0
valid time
After WR data bus delay time
After WR data bus valid time
RESET
OUT
output delay time (Note 1)
RESET
OUT
output valid time (Note 1)
The RESET
OUT
output goes “H” in sync with the rise of the
φ
clock that is anywhere between about 8 cycle and 13 cycles after
the RESET input goes “H”.
___
100
100
80
80
300
150
Symbol
Parameter
Limits
Typ.
Min.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
t
c(X
IN
)
–20
t
c(X
IN
)
–20
5
5
10
t
c(X
IN
)
–20
3t
c(X
IN
)
–20
t
c(X
IN
)
–100
t
c(X
IN
)
–100
5
5
10
0
2t
c(X
IN
)
40
10
50
10
40
10
30
t
c(X
IN
)
–40
t
c(X
IN
)
–50
10
10
30
Max.
t
c(
φ
)
t
wH(
φ
)
t
wL(
φ
)
t
d(
φ
–AH)
t
v(
φ
–AH)
t
d(
φ
–AL)
t
v(
φ
–AL)
t
d(
φ
–SYNC)
t
v(
φ
–SYNC)
t
d(
φ
–DB)
t
v(
φ
–DB)
t
wL(RD)
t
wL(WR)
t
d(AH–RD)
t
d(AH–WR)
t
d(AL–RD)
t
d(AL–WR)
t
v(RD–AH)
t
v(WR–AH)
t
v(RD–AL)
t
v(WR–AL)
t
d(WR–DB)
t
v(WR–DB)
t
d
(RESET–RESET
OUT
)
t
v(
φ
–RESET)
Test conditions
Note 1:
Fig. 32
TIMING REQUIREMENTS 2 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
(High-speed version)
SWITCHING CHARACTERISTICS 2 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
(High-Speed Version)
(V
CC
= 2.7 V, V
SS =
0 V, T
a
= –20 to 85
°
C, unless otherwise noted)
60
60
Fig. 32
Circuit for measuring output switching
characteristics (1)
Fig. 33
Circuit for measuring output switching
characteristics (2)
Measurement output pin
100pF
CMOS output
100pF
N-channel open-drain output
1k
Measurement output pin
(V
CC
= 2.7 V, V
SS =
0 V, T
a
= –20 to 85
°
C, unless otherwise noted)
MITSUBISHI MICROCOMPUTERS
3806 Group
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