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參數(shù)資料
| 型號： | M3806 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Single Chip 8 Bits Microcomputer(8位單片機(jī)) |
| 中文描述： | 單芯片8位單片機(jī)（8位單片機(jī)） |
| 文件頁數(shù)： | 51/57頁 |
| 文件大小： | 833K |
| 代理商： | M3806 |
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51
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Before
After
φ
ONW input hold time
Before
φ
data bus set up time
After
φ
data bus hold time
Before RD ONW input set up time
Before WR ONW input set up time
After RD ONW input hold time
After WR ONW input hold time
Before RD data bus set up time
After RD data bus hold time
t
su(ONW–
φ
)
t
h(
φ
–ONW)
t
su(DB–
φ
)
t
h(
φ
–DB)
t
su
(ONW–RD)
t
su
(ONW–WR)
t
h(RD–ONW)
t
h(WR–ONW)
t
su(DB–RD)
t
h(RD–DB)
Symbol
Parameter
Limits
Typ.
Min.
–20
–20
50
ns
ns
ns
ns
ns
ns
ns
ns
Unit
0
–20
–20
50
0
Max.
φ
clock cycle time
φ
clock “H” pulse width
φ
clock “L” pulse width
After
φ
AD
15
–AD
8
delay time
After
φ
AD
15
–AD
8
valid time
After
φ
AD
7
–AD
0
delay time
After
φ
AD
7
–AD
0
valid time
SYNC delay time
SYNC valid time
After
φ
data bus delay time
φ
data bus valid time
___
___
(when one-wait is valid)
After AD
15
–AD
8
RD delay time
After AD
15
–AD
8
After AD
7
–AD
0
RD delay time
___
After AD
7
–AD
0
WR delay time
After RD AD
15
–AD
8
valid time
___
After WR AD
15
–AD
8
valid time
After RD AD
7
–AD
0
valid time
___
After WR AD
7
–AD
0
valid time
After WR data bus delay time
output delay time (Note 1)
RESET
OUT
output valid time (Note 1)
The RESET
OUT
output goes “H” in sync with the fall of the
φ
clock that is anywhere between about 8 cycle and 13 cycles after
the RESET input goes “H”.
___
35
40
30
30
200
100
Symbol
Parameter
Limits
Typ.
Min.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
t
c(X
IN
)
–10
t
c(X
IN
)
–10
2
2
10
t
c(X
IN
)
–10
3t
c(X
IN
)
–10
t
c(X
IN
)
–35
t
c(X
IN
)
–40
2
2
10
0
2t
c(X
IN
)
16
5
20
5
16
5
15
t
c(X
IN
)
–16
t
c(X
IN
)
–20
5
5
15
Max.
t
c(
φ
)
t
wH(
φ
)
t
wL(
φ
)
t
d(
φ
–AH)
t
v(
φ
–AH)
t
d(
φ
–AL)
t
v(
φ
–AL)
t
d(
φ
–SYNC)
t
v(
φ
–SYNC)
t
d(
φ
–DB)
t
v(
φ
–DB)
t
wL(RD)
t
wL(WR)
t
d(AH–RD)
t
d(AH–WR)
t
d(AL–RD)
t
d(AL–WR)
t
v(RD–AH)
t
v(WR–AH)
t
v(RD–AL)
t
v(WR–AL)
t
d(WR–DB)
t
v(WR–DB)
t
d
(RESET–RESET
OUT
)
t
v(
φ
–RESET)
Test conditions
Note 1:
Fig. 32
TIMING REQUIREMENTS 1 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE (High-speed version)
(V
CC
= 4.0 to 5.5 V, V
SS =
0 V, T
a
= –20 to 85
°
C, unless otherwise noted)
SWITCHING CHARACTERISTICS 1 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
(V
CC
= 4.0 to 5.5 V, V
SS =
0 V, T
a
= –20 to 85
°
C, unless otherwise noted)
(High-speed version)
25
25
MITSUBISHI MICROCOMPUTERS
3806 Group
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| M3806 BK005 | 制造商:Alpha Wire Company 功能描述:CBL 8COND 18AWG BLK 100' |
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