參數(shù)資料
型號(hào): M38049FFHHP
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8.4 MHz, MICROCONTROLLER, PQFP64
封裝: 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁(yè)數(shù): 96/118頁(yè)
文件大?。?/td> 1202K
代理商: M38049FFHHP
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Rev.1.01
Jan 25, 2005
page 77 of 114
REJ03B0131-0101Z
3804 Group (Spec. H)
WIT instruction
STP instruction
Timing
φ (internal clock)
S
R
Q
STP instruction
S
R
Q
Main clock stop bit
S
R
Q
1/2
1/4
XIN
XOUT
XCOUT
XCIN
Interrupt request
Reset
Interrupt disable flag l
Port XC
switch bit
“ 1 ” “ 0 ”
Low-speed
mode
High-speed or
middle-speed
mode
Middle-speed mode
High-speed or
low-speed mode
Main clock division ratio
selection bits
(Note 1)
Notes 1:
Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
When low-speed mode is selected, set port Xc switch bit (b4) to “ 1 ” .
2: f(XIN)/16 is supplied as the count source to the prescaler 12 at reset. The count source before executing the STP
instruction is supplied as the count source at executing STP instruction.
3: When bit 0 of MISRG is “ 0 ” , timer 1 is set
“ 01
16
and prescaler 12 is set
“ FF
16
automatically. When bit 0 of MISRG is
“ 1 ” , set the appropriate value to them in accordance with oscillation stablizing time required by the using oscillator
because nothing is automatically set into timer 1 and prescaler 12.
4: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions.
Main clock division ratio
selection bits
(Note 1)
Prescaler 12
Timer 1
Reset or
STP instruction
(Note 2)
Divider
(Note 3)
Reset
(Note 4)
Fig. 75 System clock generating circuit block diagram
相關(guān)PDF資料
PDF描述
M38049FFHSP 8-BIT, FLASH, 8.4 MHz, MICROCONTROLLER, PDIP64
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