參數(shù)資料
型號： M38049FFHHP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8.4 MHz, MICROCONTROLLER, PQFP64
封裝： 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù)： 60/118頁
文件大?。?/td> 1202K
代理商： M38049FFHHP
Rev.1.01
Jan 25, 2005
page 44 of 114
REJ03B0131-0101Z
3804 Group (Spec. H)
3. SRDY1 output of reception side
q Note
When signals are output from the SRDY1 pin on the reception side
by using an external clock in the clock synchronous serial I/O
mode, set all of the receive enable bit, the SRDY1 output enable
bit, and the transmit enable bit to “1” (transmit enabled).
4. Setting serial I/O1 control register again
q Note
Set the serial I/O1 control register again after the transmission and
the reception circuits are reset by clearing both the transmit en-
able bit and the receive enable bit to “0.
”
5. Data transmission control with referring to transmit shift
register completion flag
q Note
After the transmit data is written to the transmit buffer register, the
transmit shift register completion flag changes from
“
1” to
“
0” with
a delay of 0.5 to 1.5 shift clocks. When data transmission is con-
trolled with referring to the flag after writing the data to the transmit
buffer register, note the delay.
6. Transmission control when external clock is selected
q Note
When an external clock is used as the synchronous clock for data
transmission, set the transmit enable bit to “1” at
“
H” of the SCLK1
input level. Also, write data to the transmit buffer register at “H” of
the SCLK1 input level.
7. Transmit interrupt request when transmit enable bit is set
q Note
When using the transmit interrupt, take the following sequence.
Set the serial I/O1 transmit interrupt enable bit to “0” (disabled).
Set the transmit enable bit to “1”.
Set the serial I/O1 transmit interrupt request bit to “0” after 1 or
more instruction has executed.
Set the serial I/O1 transmit interrupt enable bit to
“
1” (enabled).
q Reason
When the transmit enable bit is set to “1”, the transmit buffer
empty flag and the transmit shift register shift completion flag are
also set to
“
1”. Therefore, regardless of selecting which timing for
the generating of transmit interrupts, the interrupt request is gener-
ated and the transmit interrupt request bit is set at this point.
Clear both the transmit enable bit
(TE) and the receive enable bit
(RE) to
“
0”
↓
Set the bits 0 to 3 and bit 6 of the
serial I/O control register
↓
Set both the transmit enable bit
(TE) and the receive enable bit
(RE), or one of them to
“
1”
Can be set with the
LDM instruction at the
same time
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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