參數(shù)資料
型號: M38039M7L-XXXHP
廠商: Renesas Technology Corp.
英文描述: 18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
中文描述: 單芯片8位CMOS微機
文件頁數(shù): 73/119頁
文件大?。?/td> 1575K
代理商: M38039M7L-XXXHP
Rev.1.00
REJ03B0212-0100
Apr 2, 2007
Page 73 of 117
3803 Group (Spec.L)
<Notes on CPU Rewrite Mode>
Take the notes described below when rewriting the flash memory
in CPU rewrite mode.
(1) Operation speed
During CPU rewrite mode, set the system clock
φ
to 4.0 MHz or
less using the clock division ratio selection bits (bits 6 and 7 of
address 003B
16
).
(2) Instructions inhibited against use
The instructions which refer to the internal data of the flash
memory cannot be used during CPU rewrite mode.
(3) Interrupts
The interrupts cannot be used during CPU rewrite mode because
they refer to the internal data of the flash memory.
(4) Watchdog timer
If the watchdog timer has been already activated, internal reset
due to an underflow will not occur because the watchdog timer is
surely cleared during program or erase.
(5) Reset
Reset is always valid. The MCU is activated using the boot mode
at release of reset in the condition of CNV
SS
= “H”, so that the
program will begin at the address which is stored in addresses
FFFC
16
and FFFD
16
of the boot ROM area.
相關(guān)PDF資料
PDF描述
M38039M7L-XXXKP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38230GD-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38230GD-XXXHP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38230GE-XXXFP 36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
M38230GE-XXXHP 36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
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