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參數(shù)資料
| 型號： | M38039M7L-XXXHP |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | 18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 110/119頁 |
| 文件大?。?/td> | 1575K |
| 代理商： | M38039M7L-XXXHP |
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Rev.1.00
REJ03B0212-0100
Apr 2, 2007
Page 110 of 117
3803 Group (Spec.L)
A/D converter characteristics
NOTES:
1. 8-bit A/D mode: When the conversion mode selection bit (bit 7 of address 0038
16
) is “1”.
2. 10-bit A/D mode: When the conversion mode selection bit (bit 7 of address 0038
16
) is “0”.
NOTES:
1. 8-bit A/D mode: When the conversion mode selection bit (bit 7 of address 0038
16
) is “1”.
2. 10-bit A/D mode: When the conversion mode selection bit (bit 7 of address 0038
16
) is “0”.
D/A converter characteristics
NOTE:
1. Using one D/A converter, with the value in the DA conversion register of the other D/A converter being “00
16
”.
Table 26 A/D converter recommended operating conditions (Flash memory version)
(V
CC
= 2.7 to 5.5 V, V
SS
= AV
SS
= 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Conditions
Limits
Unit
Min.
2.7
2.7
2.0
Typ.
5.0
5.0
Max.
5.5
5.5
V
CC
V
CC
Power source voltage
(When A/D converter is used)
8-bit A/D mode
(1)
10-bit A/D mode
(2)
V
V
REF
AV
SS
V
IA
f(X
IN
)
Analog convert reference voltage
Analog power source voltage
Analog input voltage AN
0
-AN
15
Main clock input oscillation
frequency
(When A/D converter is used)
V
V
V
0
0
V
CC
2.7
≤
V
CC
= V
REF
<
4.0 V
0.5
MHz
4.0
≤
V
CC
= V
REF
<
4.5 V
0.5
4.5
≤
V
CC
= V
REF
≤
5.5 V
0.5
16.8
-------------------------–
)
1.05
×
--------------------------------–
3
(
)
1.05
×
Table 27 A/D converter characteristics (Flash memory version)
(V
CC
= 2.7 to 5.5 V, V
SS
= AV
SS
= 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Typ.
Unit
Min.
Max.
8
10
±2
±4
50
61
100
200
5.0
5.0
Resolution
8-bit A/D mode
(1)
10-bit A/D mode
(2)
8-bit A/D mode
(1)
10-bit A/D mode
(2)
8-bit A/D mode
(1)
10-bit A/D mode
(2)
bit
Absolute accuracy
(excluding quantization error)
2.7
≤
V
REF
≤
5.5 V
2.7
≤
V
REF
≤
5.5 V
LSB
LSB
2tc(X
IN
)
t
CONV
Conversion time
R
LADDER
I
VREF
Ladder resistor
Reference power
source input current
12
50
35
150
k
μ
A
μ
A
μ
A
at A/D converter operated V
REF
= 5.0 V
at A/D converter stopped
V
REF
= 5.0 V
I
I(AD)
A/D port input current
Table 28 D/A converter characteristics (Flash memory version)
(V
CC
= 2.7 to 5.5 V, V
REF
= 2.7 V to V
CC
, V
SS
= AV
SS
= 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Typ.
Unit
Min.
Max.
8
1.0
2.5
3
5
3.2
Resolution
Absolute accuracy
bit
%
4.0
≤
V
REF
≤
5.5 V
2.7
≤
V
REF
< 4.0 V
tsu
RO
I
VREF
Setting time
Output resistor
Reference power source input current
(1)
μ
s
k
mA
2
3.5
Table 29 Power source circuit timing characteristics (Flash memory version)
(V
CC
= 2.7 to 5.5 V, V
REF
= 2.7 V to V
CC
, V
SS
= AV
SS
= 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Typ.
Unit
Min.
2
Max.
td(P
R)
Internal power source stable time
at power-on
2.7
≤
V
CC
< 5.5 V
ms
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