參數(shù)資料
型號(hào)： M38039M6-XXXHP
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 27/119頁(yè)
文件大?。?/td> 1575K
代理商： M38039M6-XXXHP
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Rev.1.00
REJ03B0212-0100
Apr 2, 2007
Page 27 of 117
3803 Group (Spec.L)
Fig 21. Structure of interrupt-related registers
Interrupt edge selection register
(INTEDGE : address 003A
16
)
INT
0
interrupt edge selection bit
INT
1
interrupt edge selection bit
Not used (returns “0” when read)
INT
2
interrupt edge selection bit
INT
3
interrupt edge selection bit
INT
4
interrupt edge selection bit
INT
0
, INT
4
interrupt switch bit
0 : INT
00
, INT
40
interrupt
1 : INT
01
, INT
41
interrupt
Not used (returns “0” when read)
0 : Falling edge active
1 : Rising edge active
Interrupt request register 1
(IREQ1 : address 003C
16
)
INT
0
/Timer Z interrupt request bit
INT
1
interrupt request bit
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Interrupt request register 2
(IREQ2 : address 003D
16
)
CNTR
0
interrupt request bit
CNTR
1
/Serial I/O3 receive interrupt
request bit
Serial I/O2/Timer Z interrupt request bit
INT
2
interrupt request bit
INT
3
interrupt request bit
INT
4
/CNTR
2
interrupt request bit
AD converter/Serial I/O3 transmit
interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
Interrupt control register 1
(ICON1 : address 003E
16
)
INT
0
/Timer Z interrupt enable bit
INT
1
interrupt enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Interrupt control register 2
(ICON2 : address 003F
16
)
b7
b0
b7
b0
b7
b0
b7
b0
0 : Falling edge active
1 : Rising edge active
CNTR
0
interrupt enable bit
CNTR
1
/Serial I/O3 receive interrupt
enable bit
Serial I/O2/Timer Z interrupt enable bit
INT
2
interrupt enable bit
INT
3
interrupt enable bit
INT
4
/CNTR
2
interrupt enable bit
AD converter/Serial I/O3 transmit
interrupt enable bit
Not used (returns “0” when read)
(Do not write “1”.)
0 : Interrupts disabled
1 : Interrupts enabled
b7
b0
Interrupt source selection register
(INTSEL : address 0039
16
)
INT
0
/Timer Z interrupt source selection bit
0 : INT
0
interrupt
1 : Timer Z interrupt
Serial I/O2/Timer Z interrupt source selection bit
0 : Serial I/O2 interrupt
1 : Timer Z interrupt
Not used (Do not write “1”.)
INT
4
/CNTR
2
interrupt source selection bit
0 : INT
4
interrupt
1 : CNTR
2
interrupt
Not used (Do not write “1”.)
CNTR
1
/Serial I/O3 receive interrupt source selection bit
0 : CNTR
1
interrupt
1 : Serial I/O3 receive interrupt
AD converter/Serial I/O3 transmit interrupt source selection bit
0 : A/D converter interrupt
1 : Serial I/O3 transmit interrupt
(Do not write “1” to these bits simultaneously.)
b7
b0
0 : No interrupt request issued
1 : Interrupt request issued
0 : Interrupts disabled
1 : Interrupts enabled
相關(guān)PDF資料
PDF描述
M38039M6-XXXKP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38039M6-XXXSP 18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
M38039M6-XXXWG SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38039M7L-XXXHP 18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
M38039M7L-XXXKP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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M3806 BK001 制造商:Alpha Wire Company 功能描述:CBL 8COND 18AWG BLK 1000'
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