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參數(shù)資料
| 型號： | M38039M5-XXXWG |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 26/119頁 |
| 文件大?。?/td> | 1575K |
| 代理商： | M38039M5-XXXWG |
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Rev.1.00
REJ03B0212-0100
Apr 2, 2007
Page 26 of 117
3803 Group (Spec.L)
Fig 20. Interrupt control diagram
Interrupt Disable Flag
The interrupt disable flag is assigned to bit 2 of the processor
status register. This flag controls the acceptance of all interrupt
requests except for the BRK instruction. When this flag is set to
“1”, the acceptance of interrupt requests is disabled. When it is
set to “0”, acceptance of interrupt requests is enabled. This flag is
set to “1” with the SET instruction and set to “0” with the CLI
instruction.
When an interrupt request is accepted, the contents of the
processor status register are pushed onto the stack while the
interrupt disable flag remaines set to “0”. Subsequently, this flag
is automatically set to “1” and multiple interrupts are disabled.
To use multiple interrupts, set this flag to “0” with the CLI
instruction within the interrupt processing routine.
The contents of the processor status register are popped off the
stack with the RTI instruction.
Interrupt Request Bits
Once an interrupt request is generated, the corresponding
interrupt request bit is set to “1” and remaines “1” until the
request is accepted. When the request is accepted, this bit is
automatically set to “0”.
Each interrupt request bit can be set to “0”, but cannot be set to
“1”, by software.
Interrupt Enable Bits
The interrupt enable bits control the acceptance of the
corresponding interrupt requests. When an interrupt enable bit is
set to “0”, the acceptance of the corresponding interrupt request
is disabled. If an interrupt request occurs in this condition, the
corresponding interrupt request bit is set to “1”, but the interrupt
request is not accepted. When an interrupt enable bit is set to “1”,
acceptance of the corresponding interrupt request is enabled.
Each interrupt enable bit can be set to “0” or “1” by software.
The interrupt enable bit for an unused interrupt should be set to
“0”.
Interrupt Source Selection
Any of the following combinations can be selected by the
interrupt source selection register (0039
16
).
1.INT
0
or timer Z
2.CNTR
1
or Serial I/O3 reception
3.Serial I/O2 or timer Z
4.INT
4
or CNTR
2
5.A/D conversion or serial I/O3 transmission
External Interrupt Pin Selection
For external interrupts INT
0
and INT
4
, the INT
0
, INT
4
interrupt
switch bit in the interrupt edge selection register (bit 6 of address
003A
16
) can be used to select INT
00
and INT
40
pin input or
INT
01
and INT
41
pin input.
Interrupt disable flag (I)
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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| M3806 BK001 | 制造商:Alpha Wire Company 功能描述:CBL 8COND 18AWG BLK 1000' |
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