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參數(shù)資料
| 型號： | M38039M5-XXXSP |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | 9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM; Architecture: Standard Sync, Pipeline DCD; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 76/119頁 |
| 文件大小： | 1575K |
| 代理商： | M38039M5-XXXSP |
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Rev.1.00
REJ03B0212-0100
Apr 2, 2007
Page 76 of 117
3803 Group (Spec.L)
Status Register
The status register shows the operating status of the flash
memory and whether erase operations and programs ended
successfully or in error. It can be read in the following ways:
(1) By reading an arbitrary address from the User ROM area
after writing the read status register command (70
16
)
(2) By reading an arbitrary address from the User ROM area in
the period from when the program starts or erase operation
starts to when the read array command (FF
16
) is input.
Also, the status register can be cleared by writing the clear status
register command (50
16
).
After reset, the status register is set to “80
16
”.
Table 13 shows the status register. Each bit in this register is
explained below.
Sequencer status (SR7)
The sequencer status indicates the operating status of the flash
memory. This bit is set to “0” (busy) during write or erase
operation and is set to “1” when these operations ends.
After power-on, the sequencer status is set to “1” (ready).
Erase status (SR5)
The erase status indicates the operating status of erase operation.
If an erase error occurs, it is set to “1”. When the erase status is
cleared, it is reset to “0”.
Program status (SR4)
The program status indicates the operating status of write
operation.
When a write error occurs, it is set to “1”.
The program status is reset to “0” when it is cleared.
If “1” is written for any of the SR5 and SR4 bits, the read array,
program, and block erase commands are not accepted. Before
executing these commands, execute the clear status register
command (50
16
) and clear the status register.
Also, if any commands are not correct, both SR5 and SR4 are set
to “1”.
Table 13 Definition of each bit in status register
Each bit of
SRD bits
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Status name
Definition
“1”
“0”
Busy
Sequencer status
Reserved
Erase status
Program status
Reserved
Reserved
Reserved
Reserved
Ready
Terminated in error
Terminated in error
Terminated normally
Terminated normally
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M38039M5-XXXWG | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38039M6L-XXXHP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38039M6L-XXXKP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38039M6L-XXXSP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38039M6L-XXXWG | 18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M38049FFFP#U0 | 制造商:Renesas Electronics Corporation 功能描述: |
| M38049FFLHP#U0 | 制造商:Renesas Electronics Corporation 功能描述: |
| M38049RLSS | 功能描述:DEV EMULATOR CHIP RAM 2KB 64SDIP RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 內(nèi)電路編程器、仿真器以及調(diào)試器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 19/Jul/2010 標(biāo)準(zhǔn)包裝:1 系列:* 類型:* 適用于相關(guān)產(chǎn)品:* 所含物品:* |
| M3806 | 功能描述:電纜固定件和配件 LTSCG 625 BLACK RoHS:否 制造商:Heyco 類型:Cable Grips, Liquid Tight 材料:Nylon 顏色:Black 安裝方法:Cable 最大光束直徑:11.4 mm 抗拉強度: |
| M3806 BK001 | 制造商:Alpha Wire Company 功能描述:CBL 8COND 18AWG BLK 1000' |
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