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參數(shù)資料
| 型號： | M38039M5-XXXSP |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | 9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM; Architecture: Standard Sync, Pipeline DCD; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 62/119頁 |
| 文件大小： | 1575K |
| 代理商： | M38039M5-XXXSP |
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Rev.1.00
REJ03B0212-0100
Apr 2, 2007
Page 62 of 117
3803 Group (Spec.L)
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example,
because of a software run-away). The watchdog timer consists of
an 8-bit watchdog timer L and an 8-bit watchdog timer H.
Watchdog Timer Initial Value
Watchdog timer L is set to “FF
16
” and watchdog timer H is set to
“FF
16
” by writing to the watchdog timer control register (address
001E
16
) or at a reset. Any write instruction that causes a write
signal can be used, such as the STA, LDM, CLB, etc. Data can
only be written to bits 6 and 7 of the watchdog timer control
register. Regardless of the value written to bits 0 to 5, the above-
mentioned value will be set to each timer.
Bit 6 can be written only once after releasing reset. After
rewriting it is disable to write any data to this bit.
Watchdog Timer Operations
The watchdog timer stops at reset and starts to count down by
writing to the watchdog timer control register (address 001E
16
).
An internal reset occurs at an underflow of the watchdog timer
H. The reset is released after waiting for a reset release time and
the program is processed from the reset vector address.
Accordingly, programming is usually performed so that writing
to the watchdog timer control register may be started before an
underflow. If writing to the watchdog timer control register is not
performed once, the watchdog timer does not function.
Bit 6 of Watchdog Timer Control Register
When bit 6 of the watchdog timer control register is “0”, the
MCU enters the stop mode by execution of STP instruction.
Just after releasing the stop mode, the watchdog timer restarts
counting
(Note.)
. When executing the WIT instruction, the
watchdog timer does not stop.
When bit 6 is “1”, execution of STP instruction causes an
internal reset. When this bit is set to “1” once, it cannot be
rewritten to “0” by program. Bit 6 is “0” at reset.
The following shows the period between the write execution to
the watchdog timer control register and the underflow of
watchdog timer H.
Bit 7 of the watchdog timer control register is “0”:
when X
CIN
= 32.768 kHz; 32 s
when X
IN
= 16 MHz; 65.536 ms
Bit 7 of the watchdog timer control register is “1”:
when X
CIN
= 32.768 kHz; 125 ms
when X
IN
= 16 MHz; 256
μ
s
Note. The watchdog timer continues to count even while waiting for a
Fig 58. Block diagram of Watchdog timer
Fig 59. Structure of Watchdog timer control register
X
IN
Data bus
X
CIN
“10”
“00”
“01”
Main clock division
ratio selection bits
(1)
“0”
“1”
1/16
Watchdog timer H count
source selection bit
Reset
circuit
STP instruction function selection bit
Watchdog timer H (8)
“FF
16
” is set when
watchdog timer
control register is
written to.
Internal reset
Watchdog timer L (8)
“FF
16
” is set when
watchdog timer
control register is
written to.
Note 1
: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
STP instruction
RESET
b7
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction function selection bit
0: Entering stop mode by execution of STP instruction
1: Internal reset by execution of STP instruction
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(X
IN
)/16 or f(X
CIN
)/16
Watchdog timer control register
(WDTCON : address 001E
16
)
b0
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PDF描述 |
|---|---|
| M38039M5-XXXWG | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38039M6L-XXXHP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38039M6L-XXXKP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38039M6L-XXXSP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38039M6L-XXXWG | 18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M38049FFFP#U0 | 制造商:Renesas Electronics Corporation 功能描述: |
| M38049FFLHP#U0 | 制造商:Renesas Electronics Corporation 功能描述: |
| M38049RLSS | 功能描述:DEV EMULATOR CHIP RAM 2KB 64SDIP RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 內(nèi)電路編程器、仿真器以及調(diào)試器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 19/Jul/2010 標準包裝:1 系列:* 類型:* 適用于相關產(chǎn)品:* 所含物品:* |
| M3806 | 功能描述:電纜固定件和配件 LTSCG 625 BLACK RoHS:否 制造商:Heyco 類型:Cable Grips, Liquid Tight 材料:Nylon 顏色:Black 安裝方法:Cable 最大光束直徑:11.4 mm 抗拉強度: |
| M3806 BK001 | 制造商:Alpha Wire Company 功能描述:CBL 8COND 18AWG BLK 1000' |
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