參數(shù)資料
型號： M38037M8-XXXFP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機
文件頁數(shù)： 111/135頁
文件大小： 2055K
代理商： M38037M8-XXXFP
111
3803/3804 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
G
CPU reprogramming mode operation procedure
The operation procedure in CPU reprogramming mode is de-
scribed below.
< Beginning procedure >
Apply 0 V to the CNVss/V
PP
pin for reset release.
Set the CPU mode register (see Figure 103).
After CPU reprogramming mode control program is transferred to
internal RAM, jump to this control program on RAM. (The follow-
ing operations are controlled by this control program).
Set
“
1" to the CPU reprogramming mode select bit.
Apply V
PP
H to the CNV
SS
/V
PP
pin.
Wait till CNV
SS
/V
PP
pin becomes 12V.
Read the CPU reprogramming mode monitor flag to confirm
whether the CPU reprogramming mode is valid.
The operation of the flash memory is executed by software-com-
mand-writing to the flash command register .
Note:
The following are necessary other than this:
Control for data which is input from the external (serial I/O
etc.) and to be programmed to the flash memory
Initial setting for ports etc.
Writing to the watchdog timer
< Release procedure >
Apply 0 V to the CNV
SS
/V
PP
pin.
Wait till CNV
SS
/V
PP
pin becomes 0 V.
Set the CPU reprogramming mode select bit to
“
0.
”
Each software command is explained as follows.
G
Read command
When
“
00
16
" is written to the flash command register, the 3803/
3804 group enters the read mode. The contents of the corre-
sponding address can be read by reading the flash memory (For
instance, with the LDA instruction etc.) under this condition.
The read mode is maintained until another command code is written
to the flash command register. Accordingly, after setting the read
mode once, the contents of the flash memory can continuously be
read.
After reset and after the reset command is executed, the read
mode is set.
Fig. 102 Flash command register bit configuration
Fig. 103 CPU mode register bit configuration in CPU rewriting
mode
Writing of software command
<Command code>
“
00
16
”
“
40
16
”
“
C0
16
”
“
20
16
”
+
“
20
16
”
“
A0
16
”
“
FF
16
”
+
“
FF
16
”
<Software command name>
Read command
Program command
Program verify command
Erase command
Erase verify command
Reset command
Note:
The flash command register is write-only register.
Flash command register
(FCMD : address 0FFF
16
)
7
6
5
4
3
2
1
0
P
t
i
r
o
b
c
1
0
0
1
e
s
b
X
s
0
0
1
o
r
m
o
d
e
b
i
t
s
:
:
:
S
N
N
i
o
o
n
g
t
t
l
e
v
v
-
a
a
c
h
i
l
i
l
i
p
b
b
l
l
m
e
e
o
d
e
a
a
a
a
P
o
r
0
1
t
X
C
:
I
:
X
C
s
w
p
I
N
–
i
o
t
c
r
X
C
h
t
u
O
b
i
t
c
T
/
O
f
n
U
t
i
o
o
n
s
(
i
s
l
t
o
t
p
i
n
g
o
s
f
c
u
i
l
l
c
a
t
t
i
i
o
n
n
g
)
c
a
n
M0 : Oscillating
IN
–
X
OUT
) stop bit
1 : Stopped
b7 b6
0 0 :
φ
= f(X
IN
)/2 (high-speed mode)
0 1 :
φ
= f(X
IN
)/8 (middle-speed mode)
1 0 :
φ
= f(X
CIN
)/2 (low-speed mode)
1 1 : Not available
0
0
1
CPU mode register
(
C
P
U
M
:
a
d
d
r
e
s
s
0
0
3
B
1
6
)
b7
b0
S
a
0
1
c
k
p
0
1
a
g
p
p
e
a
a
s
e
e
e
l
e
c
t
i
o
n
b
i
t
:
:
g
g
F
x
t
h
i
s
b
i
t
t
o
“
1
”
.
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