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參數(shù)資料
| 型號： | M38037M6-122FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | TACHOMETER ONE CHANNEL |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 73/135頁 |
| 文件大?。?/td> | 2055K |
| 代理商： | M38037M6-122FP |
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73
3803/3804 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 67 Structure of I
2
C control register
[I
2
C Control Register (S1D)] 0014
16
The I
2
C control register (S1D: address 0014
16
) controls data com-
munication format.
Bits 0 to 2: Bit counter (BC0
–
BC2)
These bits decide the number of bits for the next 1-byte data to be
transmitted. The I
2
C interrupt request signal occurs immediately
after the number of count specified with these bits (ACK clock is
added to the number of count when ACK clock is selected by ACK
clock bit (bit 7 of S2, address 0015
16
) have been transferred, and
BC0 to BC2 are returned to
“
000
2
”
.
Also when a START condition is received, these bits become
“
000
2
”
and the address data is always transmitted and received in
8 bits.
Bit 3: I
2
C interface enable bit (ES0)
This bit enables to use the multi-master I
2
C-BUS interface. When
this bit is set to
“
0,
”
the use disable status is provided, so that the
SDA and the SCL become high-impedance. When the bit is set to
“
1,
”
use of the interface is enabled.
When ES0 =
“
0,
”
the following is performed.
PIN =
“
1,
”
BB =
“
0
”
and AL =
“
0
”
are set (which are bits of the I
2
C
status register, S1, at address 0013
16
).
Writing data to the I
2
C data shift register (S0: address 0011
16
) is
disabled.
Bit 4: Data format selection bit (ALS)
This bit decides whether or not to recognize slave addresses.
When this bit is set to
“
0,
”
the addressing format is selected, so
that address data is recognized. When a match is found between
a slave address and address data as a result of comparison or
when a general call (refer to
“
I
2
C Status Register,
”
bit 1) is re-
ceived, transfer processing can be performed. When this bit is set
to
“
1,
”
the free data format is selected, so that slave addresses are
not recognized.
Bit 5: Addressing format selection bit (10BIT SAD)
This bit selects a slave address specification format. When this bit
is set to
“
0,
”
the 7-bit addressing format is selected. In this case,
only the high-order 7 bits (slave address) of the I
2
C slave address
registers 0 to 2 are compared with address data. When this bit is
set to
“
1,
”
the 10-bit addressing format is selected, and all the bits
of the I
2
C slave address registers 0 to 2 are compared with ad-
dress data.
Bit 7: I
2
C-BUS interface pin input level selection bit (TISS)
This bit selects the input level of the SCL and SDA pins of the
multi-master I
2
C-BUS interface.
b
7
T
I
S
S
1
0
S
A
B
I
T
D
ALS ES0 BC2 B
C
1 B
C
0
b0
Not used
(return
“
0
”
when read)
I
2
C
(
S
c
D
o
n
:
t
r
d
o
l
r
r
e
e
g
s
i
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t
e
0
r
1
1
a
d
s
0
4
1
6
)
B
t
r
i
t
n
2 b
0
0
0
0
1
1
1
1
c
o
s
u
n
i
t
1 b
0
0
1
1
0
0
1
1
t
/
e
r
r
c
0
0 :
1 :
0 :
1 :
0 :
1 :
0 :
1 :
(
e
N
u
v
m
e
b
b
e
i
t
r
)
o
f
a
b
m
e
i
s
8
7
6
5
4
3
2
1
I
2
C
e
n
-
B
b
:
:
U
l
e
D
E
S
b
i
n
i
i
t
a
a
n
b
b
t
e
r
f
a
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e
a
0
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s
l
e
e
d
d
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a
:
f
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o
r
d
r
m
d
e
a
r
e
t
s
a
s
s
e
i
t
a
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g
f
c
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t
f
r
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o
m
o
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m
a
b
a
t
i
t
t
0
1
:
e
d
n
r
Addressing format
selection bit
0 : 7-bit addressing
format
1 : 10-bit addressing
format
I
2
C-BUS interface pin input
level selection bit
0 : CMOS input
1 : SMBUS input
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