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參數(shù)資料
| 型號(hào)： | M38021E1-256SS |
| 廠商： | Mitsubishi Electric Corporation |
| 元件分類(lèi)： | DC/DC變換器 |
| 英文描述： | 1 watt dc-dc converters |
| 中文描述： | 1瓦的DC - DC轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 38/62頁(yè) |
| 文件大小： | 2389K |
| 代理商： | M38021E1-256SS |
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Data Sheet U14893EJ2V0DS
41
PD703032A, 703032AY, 70F3032A, 70F3032AY
A/D Converter Characteristics (TA = –40 to +85 °C, VDD = AVDD = AVREF = 4.5 to 5.5 V, VSS = AVSS = 0 V,
Output pin load capacitance: CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Resolution
–
10
bit
ADM2 = 00H
±0.6
%FSR
Overall error
Note 1
–
ADM2 = 01H
±1.0
%FSR
Conversion time
tCONV
510
s
Zero-scale error
Note 1
–
±0.4
%FSR
ADM2 = 00H
±0.4
%FSR
Full-scale error
Note 1
–
ADM2 = 01H
±0.6
%FSR
ADM2 = 00H
±4.0
LSB
Integral linearity error
Note 2
–
ADM2 = 01H
±6.0
LSB
ADM2 = 00H
±4.0
LSB
Differential linearity error
Note 2
–
ADM2 = 01H
±6.0
LSB
Analog reference voltage
AVREF
AVREF = AVDD
4.5
5.5
V
Analog power supply voltage
AVDD
4.5
5.5
V
Analog input voltage
VIAN
AVSS
AVREF
V
AVREF input current
AIREF
12
mA
ADM2 = 00H
3
6
mA
AVDD power supply current
AIDD
ADM2 = 01H
4
8
mA
Notes 1. Excluding quantization error (
±0.05 %FSR)
2. Excluding quantization error (
±0.5 LSB)
Remarks 1. LSB: Least Significant Bit
FSR: Full Scale Range
2. ADM2: A/D converter mode register 2
Regulator (TA = –40 to +85
°°°°C, VDD = 4.0 to 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Output stabilization time
tREG
Stabilization capacitance C = 1
F
(Connected to REGC pin)
1ms
Cautions 1. Be sure to start inputting supply voltage VDD when RESET = VSS = EVSS = BVSS = 0 V (the
above state), and make RESET high level after the tREG period has elapsed.
2. If supply voltage BVDD or EVDD is input before the tREG period has elapsed following the
input of supply voltage VDD, note that data may be driven from the pins until the tREG
period has elapsed because the I/O buffers’ power supply was turned on while the circuit
was in an undefined state.
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