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參數(shù)資料
| 型號(hào)： | M38021E1-256FP |
| 廠商： | Mitsubishi Electric Corporation |
| 元件分類： | DC/DC變換器 |
| 英文描述： | 1 watt dc-dc converters |
| 中文描述： | 1瓦的DC - DC轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 36/62頁(yè) |
| 文件大?。?/td> | 2389K |
| 代理商： | M38021E1-256FP |
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Data Sheet U14893EJ2V0DS
39
PD703032A, 703032AY, 70F3032A, 70F3032AY
(10) I
2C bus mode (
PD703032AY, 70F3032AY only)
(TA = –40 to +85 °C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Normal Mode
High-Speed Mode
Parameter
Symbol
MIN.
MAX.
MIN.
MAX.
Unit
SCLn clock frequency
–
fCLK
0
100
0
400
kHz
Bus-free time (between
stop/start conditions)
<74>
tBUF
4.7
–
1.3
–
s
Hold time
Note 1
<75>
tHD:STA
4.0
–
0.6
–
s
SCLn clock low-level width
<76>
tLOW
4.7
–
1.3
–
s
SCLn clock high-level width
<77>
tHIGH
4.0
–
0.6
–
s
Setup time for start/restart
conditions
<78>
tSU:STA
4.7
–
0.6
–
s
CBUS
compatible
master
5.0
––
–
s
Data hold
time
I
2C mode
<79>
tHD:DAT
0
Note 2
–
0
Note 2
0.9
Note 3
s
Data setup time
<80>
tSU:DAT
250
–
100
Note 4
–
ns
SDAn and SCLn signal rise
time
<81>
tR
–
1000
20 + 0.1Cb
Note 5
300
ns
SDAn and SCLn signal fall
time
<82>
tF
–
300
20 + 0.1Cb
Note 5
300
ns
Stop condition setup time
<83>
tSU:STO
4.0
–
0.6
–
s
Pulse width of spike
suppressed by input filter
<84>
tSP
––
050
ns
Capacitance load of each
bus line
–
Cb
–
400
–
400
pF
Notes 1. At the start condition, the first clock pulse is generated after the hold time.
2. The system requires a minimum of 300 ns hold time internally for the SDAn signal (at VIHmin.
. of SCLn
signal) in order to occupy the undefined area at the falling edge of SCLn.
3. If the system does not extend the SCLn signal’s low-level width (tLOW), only the maximum data hold time
(tHD:DAT) needs to be satisfied.
4. The high-speed mode I
2C bus can be used in the normal-mode I2C bus system. In this case, set the
high-speed mode I
2C bus so that it meets the following conditions.
If the system does not extend the SCLn signal’s low-level width:
tSU:DAT
≥ 250 ns
If the system extends the SCLn signal’s low-level width:
Transmit the following data bit to the SDAn line prior to the SCLn line release (tRmax. + tSU:DAT =
1,000 + 250 = 1,250 ns: Normal mode I
2C bus specification).
5.
Cb: Total capacitance of one bus line (unit: pF)
Remark n = 0, 1
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