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參數(shù)資料
| 型號(hào)： | M38021E1-256FP |
| 廠商： | Mitsubishi Electric Corporation |
| 元件分類： | DC/DC變換器 |
| 英文描述： | 1 watt dc-dc converters |
| 中文描述： | 1瓦的DC - DC轉(zhuǎn)換器 |
| 文件頁數(shù)： | 25/62頁 |
| 文件大?。?/td> | 2389K |
| 代理商： | M38021E1-256FP |
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Data Sheet U14893EJ2V0DS
29
PD703032A, 703032AY, 70F3032A, 70F3032AY
(b) Clock asynchronous (TA = –40 to +85
°°°°C, VDD = 4.0 to 5.5 V, BVDD = 3.0 to 4.0 V, EVDD = 3.0 to 5.5 V,
VSS = AVSS = BVSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Address setup time (to ASTB
↓)
<10>
tSAST
0.5T – 20
ns
Address hold time (from ASTB
↓)
<11>
tHSTA
0.5T – 22
ns
Address float delay time from DSTB
↓
<12>
tFDA
0ns
Data input setup time from address
<13>
tSAID
(2 + n)T – 50
ns
Data input setup time from DSTB
↓
<14>
tSDID
(1 + n)T – 50
ns
Delay time from ASTB
↓ to DSTB↓
<15>
tDSTD
0.5T – 15
ns
Data input hold time (from DSTB
↑)
<16>
tHDID
0ns
Address output time from DSTB
↑
<17>
tDDA
(1 + i)T – 15
ns
Delay time from DSTB
↑ to ASTB↑
<18>
tDDST1
0.5T – 15
ns
Delay time from DSTB
↑ to ASTB↓
<19>
tDDST2
(1.5 + i)T – 15
ns
DSTB low-level width
<20>
tWDL
(1 + n)T – 35
ns
ASTB high-level width
<21>
tWSTH
T – 15
ns
Data output time from DSTB
↓
<22>
tDDOD
10
ns
Data output setup time (to DSTB
↑)
<23>
tSODD
(1 + n)T – 35
ns
Data output hold time (from DSTB
↑)
<24>
tHDOD
T – 25
ns
<25>
tSAWT1
n
≥ 1
1.5T – 55
ns
WAIT setup time (to address)
<26>
tSAWT2
n
≥ 1
(1.5 + n)T – 55
ns
<27>
tHAWT1
n
≥ 1
(0.5 + n)T
ns
WAIT hold time (from address)
<28>
tHAWT2
n
≥ 1
(1.5 + n)T
ns
<29>
tSSTWT1
n
≥ 1T – 45
ns
WAIT setup time (to ASTB
↓)
<30>
tSSTWT2
n
≥ 1
(1 + n)T – 45
ns
<31>
tHSTWT1
n
≥ 1nT
ns
WAIT hold time (from ASTB
↓)
<32>
tHSTWT2
n
≥ 1
(1 + n)T
ns
HLDRQ high-level width
<33>
tWHQH
T + 10
ns
HLDAK low-level width
<34>
tWHAL
T – 25
ns
Bus output delay time from HLDAK
↑
<35>
tDHAC
–6ns
Delay time from HLDRQ
↓ to HLDAK↓
<36>
tDHQHA1
(2n + 7.5)T + 25
ns
Delay time from HLDRQ
↑ to HLDAK↑
<37>
tDHQHA2
0.5T
1.5T + 25
ns
Remarks 1.
T = 1/fCPU (fCPU: CPU operating clock frequency)
2.
n: Number of wait clocks inserted in the bus cycle.
The sampling timing changes when a programmable wait is inserted.
3.
i: Number of idle states inserted after a read cycle (0 or 1).
4.
The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from
X1.
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