參數(shù)資料
型號(hào): M378T6453FZ0
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: DDR2 Unbuffered SDRAM MODULE
中文描述: 無(wú)緩沖DDR2的內(nèi)存模塊
文件頁(yè)數(shù): 4/20頁(yè)
文件大?。?/td> 382K
代理商: M378T6453FZ0
Rev. 1.3 Aug. 2005
256MB, 512MB Unbuffered DIMMs
DDR2 SDRAM
x72 DIMM Pin Configurations (Front side/Back side)
NC = No Connect, RFU = Reserved for Future Use
1. Pin173 Pin174 are reserved for 2Gb/4Gb comp. base Unbuffered DIMM.
2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.)
Pin
Front
V
REF
V
SS
DQ0
Pin
Back
V
SS
DQ4
Pin
Front
Pin
Back
V
SS
DQ28
Pin
Front
Pin
Back
V
DDQ
A3
Pin
Front
V
SS
DQS5
Pin
Back
1
121
31
DQ19
V
SS
DQ24
151
61
A4
181
91
211
DM5
2
122
32
152
62
V
DDQ
A2
V
DD
182
92
212
NC
V
SS
DQ46
3
123
DQ5
V
SS
DM0
33
153
DQ29
V
SS
DM3
63
183
A1
V
DD
93
DQS5
V
SS
DQ42
213
4
DQ1
V
SS
DQS0
124
34
DQ25
V
SS
DQS3
154
64
184
94
214
5
125
35
155
KEY
95
215
DQ47
V
SS
DQ52
6
126
NC
V
SS
DQ6
36
156
NC
V
SS
DQ30
65
V
SS
V
SS
V
DD
NC
V
DD
A10/AP
185
CK0
96
DQ43
V
SS
DQ48
216
7
DQS0
V
SS
DQ2
127
37
DQS3
V
SS
DQ26
157
66
186
CK0
V
DD
A0
V
DD
BA1
97
217
8
128
38
158
67
187
98
218
DQ53
V
SS
CK2
9
129
DQ7
V
SS
DQ12
39
159
DQ31
V
SS
CB4
68
188
99
DQ49
V
SS
SA2
219
10
DQ3
V
SS
DQ8
130
40
DQ27
V
SS
CB0
160
69
189
100
220
11
131
41
161
70
190
101
221
CK2
12
132
DQ13
42
162
CB5
71
BA0
191
V
DDQ
RAS
102
NC, TEST
2
V
SS
DQS6
222
V
SS
DM6
13
DQ9
V
SS
DQS1
133
V
SS
DM1
43
CB1
V
SS
DQS8
163
V
SS
DM8
72
V
DDQ
WE
192
103
223
14
134
44
164
73
193
S0
104
224
NC
V
SS
DQ54
15
135
NC
V
SS
CK1
45
165
NC
V
SS
CB6
74
CAS
V
DDQ
S1
194
V
DDQ
ODT0
105
DQS6
V
SS
DQ50
225
16
DQS1
V
SS
NC
136
46
DQS8
V
SS
CB2
166
75
195
106
226
17
137
47
167
76
196
NC
V
DD
V
SS
DQ36
107
227
DQ55
V
SS
DQ60
DQ61
V
SS
DM7
NC
V
SS
DQ62
18
138
CK1
V
SS
DQ14
48
168
CB7
V
SS
V
DDQ
77
ODT1
V
DDQ
V
SS
197
108
DQ51
V
SS
DQ56
228
19
NC
V
SS
139
49
CB3
V
SS
V
DDQ
CKE0
V
DD
NC
169
78
198
109
229
20
140
50
170
79
199
110
230
21
DQ10
141
DQ15
51
171
CKE1
80
DQ32
200
DQ37
111
DQ57
231
22
DQ11
V
SS
DQ16
142
V
SS
DQ20
52
172
V
DD
NC
81
DQ33
V
SS
DQS4
201
V
SS
DM4
112
V
SS
DQS7
232
23
143
53
173
82
202
113
233
24
144
DQ21
V
SS
DM2
54
174
NC
V
DDQ
A12
83
203
NC
V
SS
DQ38
114
DQS7
V
SS
DQ58
234
25
DQ17
V
SS
DQS2
145
55
NC
V
DDQ
A11
175
84
DQS4
V
SS
DQ34
204
115
235
26
146
56
176
85
205
116
236
DQ63
V
SS
VDDSPD
27
147
NC
V
SS
DQ22
DQ23
57
177
A9
V
DD
A8
A6
86
206
DQ39
V
SS
DQ44
DQ45
V
SS
117
DQ59
V
SS
SDA
SCL
237
28
DQS2
V
SS
DQ18
148
58
A7
V
DD
A5
178
87
DQ35
V
SS
DQ40
DQ41
207
118
238
29
30
149
150
59
60
179
180
88
89
90
208
209
210
119
120
239
240
SA0
SA1
Pin Description
* The VDD and VDDQ pins are tied to the single power-plane on PCB.
Pin Name
Description
Pin Name
Description
A0-A12
DDR2 SDRAM address bus
CK0, CK1, CK2
DDR2 SDRAM clocks (positive line of differential pair)
BA0, BA1
DDR2 SDRAM bank select
CK0, CK1, CK2
DDR2 SDRAM clocks (negative line of differential pair)
I
2
C serial bus clock for EEPROM
I
2
C serial bus data line for EEPROM
I
2
C serial address select for EEPROM
RAS
DDR2 SDRAM row address strobe
SCL
CAS
DDR2 SDRAM column address strobe
SDA
WE
DDR2 SDRAM wirte enable
SA0-SA2
S0, S1
DIMM Rank Select Lines
V
DD
*
V
DDQ
*
V
REF
V
SS
V
DD
SPD
NC
DDR2 SDRAM core power supply
CKE0,CKE1
DDR2 SDRAM clock enable lines
DDR2 SDRAM I/O Driver power supply
ODT0, ODT1
On-die termination control lines
DDR2 SDRAM I/O reference supply
DQ0 - DQ63
DIMM memory data bus
Power supply return (ground)
CB0 - CB7
DIMM ECC check bits
Serial EEPROM positive power supply
DQS0 - DQS8
DDR2 SDRAM data strobes
Spare Pins(no connect)
DM(0-8)
DDR2 SDRAM data masks
RESET
Not used on UDIMM
DQS0-DQS8
DDR2 SDRAM differential data strobes
TEST
Used by memory bus analysis tools (unused on memory
DIMMs)
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