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參數(shù)資料
| 型號(hào)： | M37754M8C-XXXGP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 16BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片16位微機(jī)的CMOS |
| 文件頁(yè)數(shù)： | 73/114頁(yè) |
| 文件大?。?/td> | 1116K |
| 代理商： | M37754M8C-XXXGP |
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73
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor modes are explained bellow.
Fig. 86 External memory area for each mode
Microprocessor
mode
Memory expansion
mode
2
16
to 9
16
FFFFFF
16
ROM
RAM
RAM
SFR
SFR
80
16
16
16
to 19
16
The shaded area is the external memory area.
(1) Single-chip mode [00]
The microcomputer enters the single-chip mode by connecting the
CNVss pin to Vss and starting from reset. Ports P0 to P4, P10 and
P11 all function as normal I/O ports. Port P4
2
can output clock
source
φ
1
by setting bit 7 of the processor mode register 0 to “1”.
In this mode, enable signal E is output from pin E/RD. Signal E out-
put can be stopped by setting the signal output disable select bit (bit
4 of particular function select register 1) to “1”, and it is possible to
switch the output to “L” level. Table 8 shows the function of the signal
output disable select bit’s function.
(2) Memory expansion mode [01]
The microcomputer enters the memory expansion mode by setting
the processor mode bits to “01” after connecting the CNVss pin to
Vss and starting from reset.
Pin E/RD becomes the RD output pin. RD is an read signal, and read
is performed during it is “L” level. When the internal memory area is
read, the RD output can be fixed to “H” by setting the signal output
disable select bit to “1”.
Ports P0, P1 and P2 become the output pins of addresses A
0
to A
19
and A
23
, and their I/O port function are lost.
Port P10 becomes I/O pins of data D
0
to D
7
and loses its I/O port
function. When the BYTE pin’s level is “L”, those pins function as
data I/O pins at an even address. When the level is “H”, those pins
function as data I/O pins at even and odd addresses. However, if an
internal memory area is read, external data is not input
When the BYTE pin’s level is “H” and the multiplex bus select bit (bit
5 of chip select area register; Figure 88) is “1”, port P10 functions as
follows during the bus cycle in which the external memory area cor-
responding to the chip select CS
4
are accessed:
Output pins of addresses LA
0
7
, same as low-order addresses
A
0
to A
7
, during “H” of RD or WR.
Data input/output pins at even and odd addresses during “L” of RD
or WR.
That is, it functions as a multiplex bus during that bus cycle.
Port P11 has two functions depending on the level of the BYTE pin.
When the BYTE pin level is “L”, those pins function as data D
8
to D
15
I/O pins at an odd address. The I/O port function is lost. However, if
an internal memory area is read, external data is not input. When the
BYTE pin level is “H”, port P11 functions as a programmable port
P11 similarly in the single-chip mode.
Ports P3
0
, P3
1
, P3
2
, and P3
3
become WR, BHE, ALE, and HLDA
BHE is a byte-high-enable signal which indicates that an odd ad-
dress is accessed when it is “L”.
Therefore, two bytes at even and odd addresses are accessed si-
multaneously when address A
0
is “L” and BHE is “L”.
ALE is an address-latch-enable signal. The latch is open while ALE
is “H”, so that the address signal passes through; the address is held
HLDA is a hold-acknowledge signal and is used to indicate to the
external that the microcomputer accepts HOLD input and enters
Hold state.
Ports P4
0
and P4
1
become HOLD and RDY input pins, respectively,
and their I/O port function are lost.
HOLD is a hold-request signal. It is an input signal used to make the
microcomputer enter Hold state. HOLD input is accepted when the
φ
BIU
has fallen from “H” to “L” level while the bus is not used. In Hold
state,
φ
0
to A
19
, A
23
, D
0
to D
7
, D
8
to D
15
(at BYTE
= “L”), RD, WR and BHE become floating then. These pins become
floating one cycle of
φ
BIU
later than HLDA signal becomes “L” level.
When terminating Hold state, these pins are terminated from floating
φ
BIU
later than HLDA signal becomes “H” level.
RDY is a ready signal. When this signal goes “L”,
φ
CPU
and
φ
BIU
stop at “L”. RDY is used when a slow external memory is connected
and others.
Port P4
2
becomes a normal I/O port when bit 7 of the processor
mode register 0 is “0” and becomes the clock
φ
1
output pin when bit
7 is “1”. The
φ
1
output is independent of RDY and does not stop
even when
φ
CPU
and
φ
BIU
stop owing to “L” input to the RDY pin.
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| M37754M8C-XXXHP | SINGLE-CHIP 16BIT CMOS MICROCOMPUTER |
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| M37754S4CHP | SINGLE-CHIP 16BIT CMOS MICROCOMPUTER |
| M37754 | SINGLE-CHIP 16BIT CMOS MICROCOMPUTER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37754M8C-XXXHP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16BIT CMOS MICROCOMPUTER |
| M37754S4CGP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16BIT CMOS MICROCOMPUTER |
| M37754S4CHP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M3775PR-H400CL | 制造商:Bonitron 功能描述:OVERVOLTAGE BRAKING RESISTOR |
| M3775RK-0.75A | 制造商:Bonitron 功能描述:OVERVOLTAGE BRAKING RESISTOR |
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