
MITSUBISHI MICROCOMPUTERS
M37753M8C-XXXFP, M37753M8C-XXXHP
M37753S4CFP, M37753S4CHP
20
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Fig. 14 Processor mode register 0 bit configuration
Notes 1:
Bits 2, 3, and 4 can be re-write after bit 5 (expansion function select bit) is set to “1.”
2:
After bit 5 is set to “1” once, bit 5 cannot be cleared to “0” except external reset and software reset.
3:
Bits 6 and 7 are write-only bits and undefined at read. Do not use SEB or CLB insturuction when setting bits 0–7.
Transmit clock output pin select bit
00 : Normal mode (output only to CLK
0
)
01 : Plural clocks specified; output to CLK
0
10 : Plural clocks specified; output to CLKS
0
11 : Plural clocks specified; output to CLKS
1
Internal clock stop select bit at WIT
(Note 1)
0 : Clock for peripheral function and watchdog timer are operating at WIT
1 : Internal clock except that for oscillation circuit and watchdog timer are stopped at WIT
Watchdog timer’s clock select bit
(Note 1)
0 : Exclusive clock deviding circuit output (Wf
512
, Wf
32
) is used as clock for watchdog
timer. Clock (Wf
512
, Wf
32
) for watchdog timer does not change in hold.
1 : Clock for peripheral device deviding circuit output (Pf
512
, Pf
32
) is used as clock for
watchdog timer. Clock (Pf
512
, Pf
32
) for watchdog timer changes in hold.
Watchdog timer exclusive clock dividing circuit is stopped.
7
6
5
4
3
2
1
0
Particular function select register 1 (6D
16
)
Signal output stop select bit
(Note 1)
Refer to Table 8.
Expansion function select bit
(Note 2)
Refer to Figure 62.
Pull-up select bit 0
(Note 3)
0 : With no pull-up for P5
7
, P5
6
, P5
5
, P5
4
1 : With pull-up for P5
7
, P5
6
, P5
5
, P5
4
Pull-up select bit 1
(Note 3)
0 : With no pull-up for P8
0
1 : With pull-up for P8
0
TC
1
TC
0
Fig. 15 Processor mode register 0 bit configuration
Note
: When selecting low-speed running, set bit 2 to “0.”
Processor mode bits
00 : Single-chip mode
01 : Memory expansion mode
10 : Microprocessor mode
11 : Do not select.
Internal memory access bus cycle select bit
(Note)
Internal memory access condition in high-speed running
0 : 2-
φ
access for internal RAM, 3-
φ
access for internal ROM and SFR
1 : 2-
φ
access for internal RAM, internal ROM, SFR
Software reset bit
The microcomputer is reset when this bit is set to “1”.
Interrupt priority detection time select bit
0 0 : Select 0 in Figure 13
0 1 : Select 1 in Figure 13
1 0 : Select 2 in Figure 13
Test mode bit
This bit must be “0.”
Clock
φ
1
output select bit
0 : No
φ
1
output
1 :
φ
1
output
7
6
0
5
4
3
2
1
0
Processor mode register 0 (5E
16
)