
7702/7703 Group User’s Manual
7–41
SERIAL I/O
7.4 Clock asynchronous serial I/O (UART) mode
Fig. 7.4.3 Initial setting example for relevant registers when transmitting
UART0 baud rate register (BRG0) (Address 3116)
UART1 baud rate register (BRG1) (Address 3916)
b7
b0
Set to 0016 to FF16.
Interrupt priority level select bits
When using interrupts, set these bits
to level 1–7. When disabling interrupts,
set these bits to level 0.
UART0 transmit interrupt control register (Address 7116)
UART1 transmit interrupt control register (Address 7316)
b7
1
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
b7
b0
Transmit enable bit
1: Transmission enabled
Transmission starts.
b0
UART0 transmit buffer register (Addresses 3316, 3216)
UART1 transmit buffer register (Addresses 3B16, 3A16)
b7
b0
Set transmit data here.
b15
UART0 transmit/receive mode register (Address 3016)
UART1 transmit/receive mode register (Address 3816)
b7
b0
Internal/External clock select bit
0: Internal clock
1: External clock
1 0 0: UART mode (7 bits)
1 0 1: UART mode (8 bits)
1 1 0: UART mode (9 bits)
Stop bit length select bit
0: 1 stop bit
1: 2 stop bits
Odd/Even parity select bit
0: Odd parity
1: Even parity
Parity enable bit
0: Parity disabled
1: Parity enabled
Sleep select bit
0: Sleep mode cleared (ignored)
1: Sleep mode selected
1
b2 b1 b0
UART0 transmit/receive control register 0 (Address 3416)
UART1 transmit/receive control register 0 (Address 3C16)
b7
b0
BRG count source select bits
CTS
/RTS select bit
0: CTS function selected
1: RTS function selected (CTS
function disabled)
0 0: f2
0 1: f16
1 0: f64
1 1: f512
b1 b0
(In the case of selecting the CTS function, transmission
starts when the CTSi pin’s input level is “L.”)
The CTS/RTS select bit is valid when the CTS/RTS enable
bit is “0” and the D-Ai output enable bit (bits 6 and 7 at
address 1F16) is “0.”
Note :
b8