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參數(shù)資料
| 型號(hào)： | M37542M4-XXXSP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDIP32 |
| 封裝： | 0.400 INCH, PLASTIC, SDIP-32 |
| 文件頁(yè)數(shù)： | 59/68頁(yè) |
| 文件大小： | 1191K |
| 代理商： | M37542M4-XXXSP |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7542 Group
MITSUBISHI MICROCOMPUTERS
62
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
s Timers
When n (0 to 255) is written to a timer latch, the frequency divi-
sion ratio is 1/(n+1).
When a count source of timer X, timer Y or timer Z is switched,
stop a count of timer X.
s Timer X
(1) CNTR0 interrupt active edge selection-1
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
When this bit is “0”, the CNTR0 interrupt request bit is set to “1” at
the falling edge of CNTR0 pin input signal. When this bit is “1”, the
CNTR0 interrupt request bit is set to “1” at the rising edge of
CNTR0 pin input signal.
(2) CNTR0 interrupt active edge selection-2
According to the setting value of CNTR0 active edge switch bit,
the interrupt request bit may be set to “1”.
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
Set the corresponding interrupt enable bit to “0” (disabled).
Set the active edge switch bit.
Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
Set the corresponding interrupt enable bit to “1” (enabled).
s Notes on Timer A, B
(1) Setting of timer value
When “1: Write to only latch” is set to the timer A (B) write control
bit, written data to timer register is set to only latch even if timer is
stopped. Accordingly, in order to set the initial value for timer when
it is stopped, set “0: Write to latch and timer simultaneously” to
timer A (B) write control bit.
(2) Read/write of timer A
Stop timer A to read/write its data when the system is in the follow-
ing state;
CPU operation clock source: XIN oscillation
Timer A count source: Ring oscillator output
(3) Read/write of timer B
Stop timer B to read/write its data when the system is in the fol-
lowing state;
CPU operation clock source: XIN oscillation
Timer B count source: Timer A underflow
Timer A count source: Ring oscillator output
s Notes on Output Compare
When the selected source timer of each compare channel is
stopped, written data to compare register is loaded to the com-
pare latch simultaneously.
Do not write the same data to both of compare latch x0 and x1.
When setting value of the compare latch is larger than timer set-
ting value, compare match signal is not generated. Accordingly,
the output waveform is fixed to “L” or “H” level.
However, when setting value of another compare latch is
smaller than timer setting value, this compare match signal is
generated. Accordingly, compare match interrupt occurs.
When the compare x trigger enable bit is cleared to “0” (dis-
abled), the match trigger to the waveform output circuit is
disabled, and the output waveform can be fixed to “L” or “H”
level.
However, in this case, the compare match signal is generated.
Accordingly, compare match interrupt occurs.
s Notes on Input Capture
If the capture trigger is input while the capture register (low-order
and high-order) is in read, captured value is changed between
high-order reading and low-order reading. Accordingly, some
countermeasure by software is recommended, for example
comparing the values that twice of read.
When the ring-oscillator is selected for Timer A count source,
Timer A cannot be used for the capture source timer.
Timer B cannot be used for the capture source timer when the
system is in the following state;
CPU operation clock source: XIN oscillation
Timer B count source: Timer A underflow
Timer A count source: Ring oscillator output
When writing “1” to capture latch x0 (x1) software trigger bit of
capture latch x0 and x1 at the same time, or external trigger and
software trigger occur simultaneously, the set value of capture x
status bit is undefined.
When setting the interrupt active edge selection bit and noise fil-
ter clock selection bit of external interrupt CAP0, CAP1, the
interrupt request bit may be set to “1”.
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
Set the corresponding interrupt enable bit to “0” (disabled).
Set the interrupt edge selection bit or noise filter clock selection bit.
Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
Set the corresponding interrupt enable bit to “1” (enabled).
The capture interrupt cannot be used as the interrupt for return
from stop mode. Even when the valid edge of the capture inter-
rupt is input at stop mode, system retains the stop mode. Then,
system returns from stop mode by other external interrupts, the
capture interrupt is accepted.
In this case, after system returns from stop mode, the interrupt
request bit of the corresponding capture interrupt is set to “1”.
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