參數(shù)資料
型號： M37540RSS
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機
文件頁數(shù)： 32/64頁
文件大?。?/td> 668K
代理商： M37540RSS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7540 Group
MITSUBISHI MICROCOMPUTERS
32
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Serial I/O2 operation
By writing to the serial I/O2 register (address 0031
16
) the serial I/O2
counter is set to “7”.
After writing, the S
DATA2
pin outputs data every time the transfer
clock shifts from “H” to “L”. And, as the transfer clock shifts from “L”
to “H”, the S
DATA2
pin reads data, and at the same time the contents
of the serial I/O2 register are shifted by 1 bit.
When the internal clock is selected as the transfer clock source, the
following operations execute as the transfer clock counts up to 8.
Serial I/O2 counter is cleared to “0”.
Transfer clock stops at an “H” level.
Interrupt request bit is set.
Shift completion flag is set.
Also, the S
DATA2
pin is in a high impedance state after the data transfer
is completed.
When the external clock is selected as the transfer clock source, the
interrupt request bit is set as the transfer clock counts up to 8, but
external control of the clock is required since it does not stop. Notice
that the S
DATA2
pin is not in a high impedance state on the comple-
tion of data transfer.
Also, after the receive operation is completed, the transmit/receive
shift completion flag is cleared by reading the serial I/O2 register. At
transmit, the transmit/receive shift completion flag is cleared and the
transmit operation is started by writing to serial I/O2 register.
Fig. 34 Serial I/O2 timing (LSB first)
D
0
:
When the internal clock is selected as the transfer, the S
DATA2
pin is in a high impedance state after the data transfer is completed.
Note
Synchronous clock
Serial I/O2 register
write signal
Transfer clock
(Note)
S
DATA2
at serial I/O2
input receive
S
DATA2
at serial I/O2
output transmit
Serial I/O2 interrupt request bit set
Transmit/receive shift completion flag set
D
1
D
2
D
3
D
4
D
5
D
6
D
7
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