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參數(shù)資料
| 型號(hào)： | M37534M4-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO36 |
| 封裝： | 8.40 X15 MM, 0.80 MM PITCH, PLASTIC, SSOP-36 |
| 文件頁數(shù)： | 27/58頁 |
| 文件大?。?/td> | 753K |
| 代理商： | M37534M4-XXXFP |
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7534 Group
Rev.3.00
Oct 23, 2006
page 31 of 53
REJ03B0099-0300
Serial I/O2 operation
By writing to the serial I/O2 register(address 003116) the serial I/O2
counter is set to “7”.
After writing, the SDATA pin outputs data every time the transfer clock
shifts from a high to a low level. And, as the transfer clock shifts from
a low to a high, the SDATA pin reads data, and at the same time the
contents of the serial I/O2 register are shifted by 1 bit.
When the internal clock is selected as the transfer clock source, the
following operations execute as the transfer clock counts up to 8.
Serial I/O2 counter is cleared to “0”.
Transfer clock stops at an “H” level.
Interrupt request bit is set.
Shift completion flag is set.
Also, the SDATA pin is in a high impedance state after the data trans-
fer is complete. Refer to Figure 34.
When the external clock is selected as the transfer clock source, the
interrupt request bit is set as the transfer clock counts up to 8, but
external control of the clock is required since it does not stop. Notice
that the SDATA pin is not in a high impedance state on the completion
of data transfer.
Fig. 34 Serial I/O2 timing (LSB first)
D0
Note : When the internal clock is selected as the transfer and the direction register of P1 3/SDATA pin is set to the input mode,
Synchronous clock
Serial I/O2 register
write signal
Transfer clock
(Note)
SDATA at serial I/O2
input receive
SDATA at serial I/O2
output transmit
Serial I/O2 interrupt request bit set
D1
D2
D3
D4
D5
D6
D7
the SDATA pin is in a high impedance state after the data transfer is completed.
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相關(guān)代理商/技術(shù)參數(shù) |
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| M37534M4-XXXGP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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