參數(shù)資料
型號: M37534M4-XXXFP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO36
封裝: 8.40 X15 MM, 0.80 MM PITCH, PLASTIC, SSOP-36
文件頁數(shù): 21/58頁
文件大?。?/td> 753K
代理商: M37534M4-XXXFP
7534 Group
Rev.3.00
Oct 23, 2006
page 26 of 53
REJ03B0099-0300
Fig. 29 Structure of serial I/O1-related registers (3)
b7
b0
USB transmit data byte number set register 1
(EP1BYTE: address 002216)
Set a number of data byte for transmitting with endpoint 1.
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
Not used (return “0” when read)
b7
b0
USB transmit data byte number set register 0
(EP0BYTE: address 002116)
Set a number of data byte for transmitting with endpoint 0.
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
Not used (return “0” when read)
b7
b0
USB address register
(USBA: address 002516)
Set an address allocated by the USB host.
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
Not used (returns “1” when read)
USB PID control register 1
(EP1PID: address 002416)
Not used (return “1” when read)
Endpoint 1 PID selection flag
1x: IN token interrupt of DATA0/1 is valid
01: STALL handshake is valid for IN token
00: NAK handshake is valid for IN token
b7
b0
x: any data
b6
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
b7
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Clear
b7
b0
USB PID control register 0
(EP0PID: address 002316)
Not used (return “1” when read)
Endpoint 0 enable flag
0: Endpoint 0 invalid
1: Endpoint 0 valid
Endpoint 0 PID selection flag
1xxx: IN token interrupt of DATA0/1 is valid
01xx: STALL handshake is valid for IN token
00xx: NAK handshake is valid for IN token
xxx1: STALL handshake is valid for OUT token (Note)
xx10: ACK handshake is valid for OUT token
xx00: NAK handshake is valid for OUT token
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
b4, b5, b6
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
b7
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Clear
x: any data
Note: In the status stage of the control read transfer, when PID
of data packet = DATA0 (incorrect PID), this bit is set forcibly
by hardware and STALL handshake is valid.
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