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HARDWARE
7531 Group User’s Manual
1-10
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The 7531 group uses the standard 740 family instruction set. Refer to
the table of 740 family addressing modes and machine instructions or
the 740 Family Software Manual for details on the instruction set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instructions cannot be used.
The MUL and DIV instructions cannot be used.
The WIT and STP instructions can be used.
The central processing unit (CPU) has the six registers.
Accumulator (A)
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
Index register X (X), Index register Y (Y)
Both index register X and index register Y are 8-bit registers. In the
index addressing modes, the value of the OPERAND is added to the
contents of register X or register Y and specifies the real address.
When the T flag in the processor status register is set to “1”, the value
contained in index register X becomes the address for the second
OPERAND.
Stack pointer (S)
The stack pointer is an 8-bit register used during sub-routine calls and
interrupts. The stack is used to store the current address data and
processor status when branching to subroutines or interrupt routines.
The lower eight bits of the stack address are determined by the con-
tents of the stack pointer. The upper eight bits of the stack address are
determined by the Stack Page Selection Bit. If the Stack Page Selec-
tion Bit is “0”, then the RAM in the zero page is used as the stack area.
If the Stack Page Selection Bit is “1”, then RAM in page 1 is used as
the stack area.
The Stack Page Selection Bit is located in the SFR area in the zero
page. Note that the initial value of the Stack Page Selection Bit varies
with each microcomputer type. Also some microcomputer types have
no Stack Page Selection Bit and the upper eight bits of the stack ad-
dress are fixed. The operations of pushing register contents onto the
stack and popping them from the stack are shown in Figure 10.
Program counter (PC)
The program counter is a 16-bit counter consisting of two 8-bit regis-
ters PCH and PCL. It is used to indicate the address of the next instruc-
tion to be executed.
Fig. 9 740 Family CPU register structure
b7
b0
X
b7
b0
S
b7
b0
Y
b7
b0
PCL
Processor Status Register (PS)
Carry Flag
b7
b0
b7
b0
A
b15
PCH
Zero Flag
Interrupt Disable Flag
Decimal Mode Flag
Break Flag
Index X Mode Flag
Overflow Flag
Negative Flag
Program Counter
Stack Pointer
Index Register Y
Index Register X
Accumulator
C
Z
I
D
B
T
V
N
FUNCTIONAL DESCRIPTION