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參數(shù)資料
| 型號： | M35500AFP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | FLD (VFD) Controller(真空熒光顯示器控制器) |
| 中文描述： | 弗倫德（VFD）的控制器（真空熒光顯示器控制器） |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 169K |
| 代理商： | M35500AFP |
3
MITSUBISHI <DIGITAL ASSP>
M35500AFP/BGP
FLD(VFD) CONTROLLER
Table. 1. Pin description
Function
Apply voltage of 5 V to V
CC
, and 0 V to V
SS
.
Applies voltage supplied to pull-down resistors.
RC oscillator pins for system clock.
Reset input pin for active “L”.
Internal pull-up resistors connected between the RESET and V
CC
pins.
Serial transfer is possible by inputting “L” signal.
Clock for serial transfer is input.
Read a clock twice with 2 MHz sampling clock and judge if it is a noise or not.
Serial data is output.
During reset it is in high-impedance state.
Serial data is input.
Read a clock twice with 2 MHz sampling clock and judge if it is a noise or not.
Pin for ordinary output or digit output.
At reset this port is set to V
EE
level through a pull-down resistor.
Pin for digit output or segment output.
At reset this port is set to V
EE
level through a pull-down resistor.
Pin for segment output.
At reset this port is set to V
EE
level through a pull-down resistor.
Output
Output
N-channel
open-drain
P-channel
open-drain
P-channel
open-drain
P-channel
open-drain
Pin
V
CC
, V
SS
V
EE
X
IN
X
OUT
RESET
CS
S
CLK
S
OUT
S
IN
DIG
0
/P0 –
DIG
7
/P7
DIG
8
/SEG
17
–
DIG
17
/SEG
8
SEG
0
– SEG
7
Name
Power source
Pull-down
power source
Clock input
Clock output
RESET input
Chip select
Serial clock
Serial output
Serial input
Digit/Port
Digit/Segment
Segment
Input
Input
CMOS input
CMOS input
CMOS input
Noise filter
CMOS input
Noise filter
PORT BLOCK
Fig. 3. Port block diagram
PIN DESCRIPTION
(2) Digit pin
latch
V
EE
Dimmer signal
(Note)
Shift signal from high-order
Shift signal to low-order
(3) Segment pin
latch
V
EE
Dimmer signal
(Note)
Segment data
(6) S
IN
, S
CLK
pin
Serial input
Serial clock input
Noise filter
(1) Digit/Port pin
Digit/Segment pin
Data bus
Segment data
latch
V
EE
Dimmer signal
(Note)
Shift signal from high-order
Shift signal to low-order
8
High-breakdown-voltage P-channel transistor
Note:
Dimmer signal is for setting the Toff time.
S
OUT
signal
(4) S
OUT
pin
(5) CS pin
CS input
A-D conversion input
(7) A-D input
Noise filter
8
8
8
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