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Rev.1.02
Nov 26, 2008
REJ03B0224-0102
455A Group
(6) Clock control register MR
Register MR controls system clock and operation mode
(frequency division of system clock). Set the contents of this
register through register A with the TMRA instruction. In
addition, the TAMR instruction can be used to transfer the
contents of register MR to register A.
(7) Clock control register RG
Register RG controls the start/stop of each oscillation circuit. Set
the contents of this register through register A with the TRGA
instruction.
Note 1. R” represents read enabled, and “W” represents write enabled.
Note 2. The stopped clock cannot be selected for system clock.
Note 3. The oscillation circuit selected for system clock cannot be stopped.
Table 28 Clock control registers
Clock control register MR
at reset : 11002
at power down : state retained
R/W
TAMR/TMRA
MR3
Operation mode selection bits
MR3 MR2
Operation mode
0
Through mode
0
1
Frequency divided by 2 mode
MR2
1
0
Frequency divided by 4 mode
1
Frequency divided by 8 mode
MR1
System clock selection bits (Note 2)
MR1 MR0
System clock
0
f(HSOCO)
MR0
0
1
f(XIN)
10
f(XCIN)
1
f(LSOCO)
Clock control register RG
at reset : 10002
at power down : state retained
W
TRGA
RG3
Low-speed on-chip oscillator (f(LSOCO))
0
Low-speed on-chip oscillator (f(LSOCO)) oscillation available
1
Low-speed on-chip oscillator (f(LSOCO)) oscillation stop
RG2
Sub-clock (f(XCIN)) control bit (Note 3) 0
Sub-clock (f(XCIN)) oscillation available, ports D6 and D7 not selected
1
Sub-clock (f(XCIN)) oscillation stop, ports D6 and D7 selected
RG1
Main-clock (f(XIN)) control bit (Note 3) 0
Main clock (f(XIN)) oscillation available
1
Main clock (f(XIN)) oscillation stop
RG0
High-speed on-chip oscillator (f(HSOCO))
0
High-speed on-chip oscillator (f(HSOCO)) oscillation available
1
High-speed on-chip oscillator (f(HSOCO)) oscillation stop