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參數(shù)資料
| 型號(hào)： | M34524MC-XXXFP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64 |
| 文件頁(yè)數(shù)： | 83/163頁(yè) |
| 文件大?。?/td> | 1235K |
| 代理商： | M34524MC-XXXFP |
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Rev.2.00
Jul 27, 2004
page 24 of 159
REJ03B0091-0200Z
4524 Group
(6) Interrupt control registers
Interrupt control register V1
Interrupt enable bits of external 0, timer 1 and timer 2 are as-
signed to register V1. Set the contents of this register through
register A with the TV1A instruction. The TAV1 instruction can be
used to transfer the contents of register V1 to register A.
Interrupt control register V2
The timer 3, timer 5, A/D, Timer 4 and serial I/O interrupt enable
bit is assigned to register V2. Set the contents of this register
through register A with the TV2A instruction. The TAV2 instruction
can be used to transfer the contents of register V2 to register A.
Table 6 Interrupt control registers
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: These instructions are equivalent to the NOP instruction.
3: Select the timer 4 interrupt or serial I/O interrupt by the timer 4, serial I/O interrupt source selection bit (I30).
(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt en-
able bits (V10–V13, V20–V23), and interrupt request flag are “1.”
The interrupt actually occurs 2 to 3 machine cycles after the ma-
chine cycle in which all three conditions are satisfied. The interrupt
occurs after 3 machine cycles when the interrupt conditions are
satisfied on execution of two-cycle instructions or three-cycle in-
structions. (Refer to Figure 16).
Interrupt disabled (SNZT4, SNZSI instruction is valid)
Interrupt enabled (SNZT4, SNZSI instruction is invalid) (Note 2)
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid) (Note 2)
Interrupt disabled (SNZT5 instruction is valid)
Interrupt enabled (SNZT5 instruction is invalid) (Note 2)
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid) (Note 2)
V13
V12
V11
V10
V23
V22
V21
V20
Timer 4, serial I/O interrupt enable bit (Note 3)
A/D interrupt enable bit
Timer 5 interrupt enable bit
Timer 3 interrupt enable bit
Interrupt control register V2
at power down : 00002
at reset : 00002
0
1
0
1
0
1
0
1
Interrupt control register V1
Timer 2 interrupt enable bit
Timer 1 interrupt enable bit
External 1 interrupt enable bit
External 0 interrupt enable bit
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid) (Note 2)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid) (Note 2)
Interrupt disabled (SNZ1 instruction is valid)
Interrupt enabled (SNZ1 instruction is invalid) (Note 2)
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid) (Note 2)
0
1
0
1
0
1
0
1
at power down : 00002
at reset : 00002
R/W
TAV1/TV1A
R/W
TAV2/TV2A
I30
Timer 4, serial I/O interrupt source selection
bit
Interrupt control register I3
R/W
TAI3/TI3A
at power down : state retained
at reset : 02
Timer 4 interrupt valid, serial I/O interrupt invalid
Serial I/O interrupt valid, timer 4 interrupt invalid
0
1
Interrupt control register I3
The timer 4, serial I/O interrupt source selection bit is assigned to
register I3. Set the contents of this register through register A
with the TI3A instruction. The TAI3 instruction can be used to
transfer the contents of register I3 to register A.
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